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SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions.
TM
memory
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50405-1E
3 Stacked MCP (Multi-Chip Package) FLASH & FLASH & FCRAM
CMOS
128M (x16) Burst FLASH MEMORY & 128M (x16) Burst FLASH MEMORY & 128M (x16) Page/Burst Mobile FCRAMTM
MB84SF6H6H6L2-70
s FEATURES
* Power supply voltage Flash _1 & 2: VCCf = 1.65 V to 1.95 V FCARM: VCCr = 2.5 V to 3.1 V, VCCQr = 1.65 V to 1.95 V * High performance 11 ns maximum Burst read access time, 56 ns maximum random access time (Flash_1 & Flash_2) 11 ns maximum Burst read access time, 70 ns maximum random access time (FCRAMTM) (Continued) Flash_1 & Flash_2 Supply Voltage (V) I/O Supply Voltage (V) Max Latency Time (ns) Synchronous/ Max Burst Access Time (ns) Burst Max OE Access Time (ns) Max Address Access Time (ns) Max CE Access Time (ns) Asynchronous Max OE Access Time (ns) Max Page Access Time (ns)
VCCf_1 & 2* = 1.8 V
+0.15V -0.15V
s PRODUCT LINEUP
FCRAM
VCCr* = 3.0 V
+0.10V -0.50V
VCCQr = 1.65 V to 1.95 V 71 11 11 56 56 11 --
VCCQr = 1.65 V to 1.95 V -- 11 -- 70 70 40 20
*: All of VCCf_1, VCCf_2 and VCCr must be the same level when either part is being accessed.
s PACKAGE
115-ball plastic FBGA
BGA-115P-M03
MB84SF6H6H6L2-70
* Operating Temperature -30 C to +85 C * Package 115-ball BGA -- FLASH MEMORY_1 & FLASH MEMORY_2 * * * * 0.13 m process technology Single 1.8 volt read, program and erase (1.65 V to 1.95 V) Simultaneous Read/Write operation (Dual Bank) FlexBankTM *1 Bank A: 16Mbit (4 Kwords x 8 and 32 Kwords x 31) Bank B: 48Mbit (32 Kwords x 96) Bank C: 48Mbit (32 Kwords x 96) Bank D: 16Mbit (4 Kwords x 8 and 32 Kwords x 31) High Performance Burst frequency reach at 66MHz Burst access times of 11 ns @ 30 pF at industrial temperature range Asynchronous random access times of 56 ns (at 30 pF) Programmable Burst Interface Linear Burst: 8, 16, and 32 words with wrap-around Minimum 100,000 program/erase cycles Sector Erase Architecture Eight 4 Kwords, two hundred fifty-four 32 Kwords sectors, eight 4 Kwords sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase. WP Input Pin (WP_1, WP_2) At VIL, allows protection of "outermost" 4x4 K words on low, high end or both ends of boot sectors, regardless of sector protection/unprotection status. Accelerate Pin (ACC) At VACC, increases program performance. ; all sectors locked when ACC = VIL Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Ready Output (RY/BY) In Synchronous Mode, indicates the status of the Burst read. In Asynchronous Mode, indicates the status of the internal program and erase function. Automatic sleep mode When address remain stable, the device automatically switches itself to low power mode Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device Hardware reset pin (RESET) Hardware method to reset the device for reading array data Please refer to "MBM29BS12DH" Datasheet in deteiled function (Continued)
*
* * *
*
* * * * *
* * * *
2
MB84SF6H6H6L2-70
(Continued)
-- FCRAMTM *3 * Power dissipation Operating : 35 mA Max Standby : 300 A Max (no CLK) * Various Partial Power Down mode Sleep : 10 A Max 16M Partial : 120 A Max 32M Partial : 150 A Max * Power down control by CE2r * 8 words Page Read Access Capability * Burst Read/Write Access Capability * Byte write control: LB(DQ7 to DQ0), UB(DQ15 to DQ8) *1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. *3: FCRAMTM is a trademark of Fujitsu Limited, Japan.
3
MB84SF6H6H6L2-70
s PIN ASSIGNMENT
(Top View) Marking side
A10 N.C. A9 N.C.
B10 N.C. B9 N.C.
C10 N.C. C9 N.C. C8 N.C. C7 N.C. C6 N.C. C5 CEf_2 C4 CLK C3 N.C.
D10 N.C. D9 N.C. D8 A11 D7 A8 D6 WE D5 ACC D4 LB D3 A7 D2 WP_1 D1 N.C.
E10 N.C. E9 A15 E8 A12 E7 A19 E6 CE2r E5 RESET E4 UB E3 A6 E2 A3 E1 N.C.
F10 N.C. F9 A21 F8 A13 F7 A9 F6 A20 F5 RY/BY F4 A18 F3 A5 F2 A2 F1 N.C.
G10 N.C. G9 A22 G8 A14 G7 A10 G6 WP_2 G5 N.C. G4 A17 G3 A4 G2 A1 G1 N.C.
H10 N.C. H9 A16 H8 N.C. H7 DQ6 H6 N.C. H5 VCCr H4 DQ1 H3 VSS H2 A0 H1 N.C.
J10 N.C. J9 N.C. J8 DQ15 J7 DQ13 J6 DQ4 J5 DQ3 J4 DQ9 J3 OE J2 CEf_1 J1 N.C.
K10 N.C. K9 VSS K8 DQ7 K7 DQ12 K6 VCCQr K5 VCCf_1 K4 DQ10 K3 DQ0 K2 CE1r K1 N.C.
L10 N.C. L9 N.C. L8 DQ14 L7 DQ5 L6 N.C. L5 DQ11 L4 DQ2 L3 DQ8 L2 N.C. L1 N.C.
M10 N.C.. M9 N.C. M8 N.C. M7 N.C. M6 N.C. M5 VCCf_2 M4 VSS M3 N.C. M2 N.C. M1 N.C.
N10 N.C. N9 N.C.
P10 N.C. P9 N.C.
A2 N.C. A1 N.C.
B2 N.C. B1 N.C.
C2 ADV
N2 N.C. N1 N.C.
P2 N.C. P1 N.C.
(BGA-115P-M03)
4
MB84SF6H6H6L2-70
s PIN DESCRIPTION
Pin name A22 to A0 DQ15 to DQ0 CEf_1 CEf_2 CE1r CE2r OE WE RY/BY UB LB ADV CLK RESET WP_1 WP_2 ACC N.C. VSS VCCf_1 VCCf_2 VCCr VCCQr Input/ Output I I/O I I I I I I O I I I I I I I I -- Power Power Power Power Power Address Inputs (Common) Data Inputs/Outputs (Common) Chip Enable (Flash_1) Chip Enable (Flash_2) Chip Enable (FCRAM) Chip Enable (FCRAM) Output Enable (Common) Write Enable (Common) Ready Output. (In asynchronous mode, RY/BY Output) / (Low Active) (Flash_1 & Flash_2) & Wait Signal Output (FCRAM) Upper Byte Control (FCRAM) Lower Byte Control (FCRAM) Address Data Valid (Common) CLK Input (Common) Hardware Reset Pin/Sector Protection Unlock (Flash_1& Flash_2) Write Protect (Flash_1) Write Protect (Flash_2) Program Acceleration (Flash_1&2) No Internal Connection Device Ground (Common) Device Power Supply (Flash_1) Device Power Supply (Flash_2) Device Power Supply (FCRAM) I/O Power Supply (FCRAM) Description
5
MB84SF6H6H6L2-70
s BLOCK DIAGRAM
VCCf_1
VSS
CEf_1 RESET WP_1 OE WE CLK ADV ACC
CEf_1 RESET WP OE WE CLK ADV RY/BY RY/BY
128 Mbit Burst Flash Memory
DQ15 to DQ0
A22 to A0
VCCf_2
VSS
CEf_2
CEf_2 RESET RY/BY
WP_2
WP OE WE CLK ADV
128 Mbit Burst Flash Memory
DQ15 to DQ0
DQ15 to DQ0
A22 to A0
A22 to A0
VCCr
VCCQr
VSS
CE1r CE2r UB LB
CE1r WAIT WAIT CE2r UB LB OE WE CLK ADV
128 Mbit Burst FCRAM
DQ15 to DQ0
A22 to A0
6
MB84SF6H6H6L2-70
s DEVICE BUS OPERATIONS
* Asynchronous Operation RY/BY(WAIT)
High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z
DQ15 to DQ8
DQ7 to DQ0
Operation
A22 to A0
RESET
CEf_1
CEf_2
WP_1
WP_2 X X X X X X X X X X X X X L*5 X X X
CE1r
CE2r
Full Standby Output Disable*1 Flash_1 or 2 Asynchronous Read Addresses Latched*2 Flash_1or 2 Write - WE address latched*4 Flash_1or 2 Write - ADV address latched*4 FCRAM NO Read FCRAM Read (Upper Byte) FCRAM Read (Lower Byte) FCRAM Read (Word) FCRAM Page Read FCRAM No Write FCRAM Write (Upper Byte) FCRAM Write (Lower Byte) FCRAM Write (Word) Flash_1 Boot Sector Write Protection*5 Flash_2 Boot Sector Write Protection*5 Flash_1 &2 All Sector Write Protection*5 Flash_1 & Flash_2 RESET FCRAM Power Down*8
H H H L L H L H L H H H H H H H H H H X X X X X
H H L H H
H L H H H
H H H H H
X H H H L
X H H H H
X X X X X
X X X X X
X X*3 X X
Addr In
High-Z High-Z
X X X X L
H H
X X
High-Z High-Z
DOUT
DOUT
H
X
L H L H L H H H H H H H H H X X X X X H L L L L L L L L L X X H H X H H H H H H H*9 H*9 H*9 H*9 X X H H L H L L L L L H*9 H*9 H*9 H*9 X X X X X H H H H H L L L L X X X X X X H H L L X H L H L H H H L X X
Addr In Addr In
DIN
DIN
L
H
X*5 X*5 H*5
DIN
DIN
H *6 *6 *6 *6 *6 *6 *6 *6 *6 X X X X X X X X X X X X X X H H H L X
X*5 X*5 H*5 X X X X X X X X X L*5 X X X X X X X X X X X X X X X L*5 X X
Valid High-Z High-Z Valid High-Z Output Valid Valid Output High-Z Valid Valid Output Output Valid Valid
L/H L/H Valid H H L L X X X X X H L H L X X X X X
*7
*7
Valid Invalid Invalid Valid Invalid Valid Valid
Input Valid Input Valid Input Valid Invalid Input Valid
X X X X X
X X X
X X X
High-Z High-Z High-Z High-Z
(Continued)
7
ACC X X X
ADV
WE
UB
OE
LB
MB84SF6H6H6L2-70
(Continued) Legend : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance. See "* DC Characteristics" in "s ELECTRICAL CHARACTERISTICS" for voltage levels.
*1 : FCRAM Output Disable Mode(CE1r = "L")Should not be kept this logic condition longer than 4 ms. Please contact local FUJITSU representative for the relaxation of 4 ms limitation. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Can be either VIL or VIH but must be valid before Read or Write. *4 : Write Operation: at asynchronous mode, addresses are latched on the last falling edge of WE pulse while ADV is held low or rising edge of ADV pulse whichever comes first. Data is latched on the 1st rising edge of WE. *5 : At WP=VIL, SA0 to SA3 and SA266 to SA269 are protected. At ACC=VIL, all sectors are protected. *6 : "L" for address pass through and "H" for address latch on the rising edge of ADV. *7 : Output is either Valid or High-Z depending on the level of UB and LB input. *8 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Partial Size. Refer to "2. Functional Description * Power Down" in "s 128M FCRAM CHARACTERISTICS for MCP" for the details. *9 : OE can be VIL during Write operation if the following conditions are satisfied; (1) Write pulse is initiated by CE1r (refer to CE1r Controlled Write timing), or cycle time of the previous operation cycle is satisfied. (2) OE stays VIL during Write cycle.
8
MB84SF6H6H6L2-70
* Synchronous Operation RY/BY(WAIT)
High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z High -Z*14 Output Valid High -Z*15
DQ15 to DQ8
DQ7 to DQ0
Operation
A22 to A0
RESET
CEf_1
CEf_2
CLK*1
WP_1
WP_2 X X X X X
X X X X
CE1r
CE2r
Flash_1 or 2 Load Starting Burst Address (CLK latch)*3 Flash_1 or 2 Advance Burst to next address with appropriate Data presented on the Data Bus*3 Flash_1 or 2 Terminate current Burst read cycle Flash_1 or 2 Terminate current Burst read cycle and start new Burst read cycle Flash_1 or 2 Burst Suspend Flash_1 or 2 Synchronous Write - WE address latched*12 Flash_1 or 2 Synchronous Write - CLK address latched*12 Flash_1 or 2 Synchronous Write -ADV address latched *12 Flash_1& 2 Terminate current Burst read via RESET FCRAM Start Address*2 Latch FCRAM Advance Burst Read to Next Address*2 FCRAM Burst Read Suspend*2
L H L H
H L H L H H L H X X H H X H X X
Addr In
X
X
*9
H
X
X
DOUT
DOUT
*9
H
H
X
H L H L H L H L H L L
H H L H L H L H L H L
H
H
X
H
X
X
X
X
HIGHZ
*9
X
H
X
H
H
X
H
X
X
Addr In
DOUT
DOUT
*9
H
X
H
H
H
H
X
X
X Addr In Addr In Addr In
High-Z High-Z
X
H
H
X
H
H
H
L
X
X
DIN
DIN
H/L
L
H
X*4 X*4 H*4
H
H
H
X
X
DIN
DIN
*9
L
H
X*4 X*4 H*4
H
H
H
X
X
DIN
DIN
H/L
H
X*4 X*4 H*4
X
X
H
H
X
H
X
X
X
HIGHZ
HIGHZ
X
X
L
X
H
H
L
H
X*5 X*5 X*6 X*6
Valid *7
HighZ*8
HighZ*8
X
X
*9
H H L H L H X*6 X*6 X
Output Output Valid Valid *10 *10
H
X
X
*9
H X X X
H
H
L
H
H
H
X*6 X*6
X
High-Z High-Z
*9
(Continued)
ACC X X X X X
X X X
ADV
WE
OE
UB
LB
9
MB84SF6H6H6L2-70
(Continued)
RY/BY(WAIT)
High -Z*16 High -Z*15 High -Z High -Z
DQ15 to DQ8
DQ7 to DQ0
Operation
A22 to A0
RESET
CEf_1
CEf_2
CLK*1
WP_1
WP_2
X X X X
CE1r
CE2r
FCRAM Advance Burst Write to Next Address*2 FCRAM Burst Write Suspend*2 FCRAM Terminate Burst Read FCRAM Terminate Burst Write
H
H
L
H
H
L*13
X*6
X*6
X
Input Valid *11
Input Valid *11 Input Invali d HighZ HighZ
H
X
X
*9
H X X X
H
H
L
H
H
H*13
X*6
X*6
X
Input Invalid HighZ HighZ
*9
X H X X X
H
H
H
L
H
X*6
X*6
X
H
H
H
H
L
X*6
X*6
X
X
H
X
X
Legend : L = VIL, H = VIH, X can be either VIL or VIH, = positive edge, = positive edge of Low pulse, High-Z = High Impedance. See "* DC Characteristics" in "s ELECTRICAL CHARACTERISTICS" for voltage levels. *1 : Default state is "X" after power-up. *2 : FCRAM Output Disable Mode(CE1r = "L")Should not be kept this logic condition longer than 4 ms. Please contact local FUJITSU representative for the relaxation of 4 ms limitation. *3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4 : At WP=VIL, SA0 to SA3 and SA266 to SA269 are protected. At ACC=VIL, all sectors are protected. *5 : Can be either VIL or VIH except for the case the both of OE and WE are VIL. It is prohibited to bring the both of OE and WE to VIL. *6 : Can be either VIL or VIH but must be valid before Read or Write is determined. And once UB and LB inputs are determined, it must not be changed until the end of burst. *7 : Once valid address is determined, input address must not be changed during ADV=L. In case A22, "H" must not be changed until end of burst. *8 : If OE=L, output is either Invalid or High-Z depending on the level of UB and LB input. If WE=L, Input is Invalid. If OE=WE=H, output is High-Z. *9 : Valid clock edge shall be set on either positive or negative edge through CR (Configration Register) Set. *10 : Output is either Valid or High-Z depending on the level of UB and LB input. *11 : Input is either Valid or Invalid depending on the level of UB and LB input. *12 : Write Operation: at synchronous mode, addresses are latched on the falling edge of WE while ADV is held low, active edge of CLK while ADV is held low or rising edge of ADV whichever happens first. Data is latched on the 1st rising edge of WE. *13 : When device is operationg in "WE Single Clock Pulse Control" mode, WE is don't care once write operation is determined by WE Low Pulse at the begginig of write access together with address latcing. Write suspend feature is not supported in "WE Single Clock Pulse Control" mode. *14 : Output is either High-Z or Invalid depending on the level of OE and WE input. *15 : Keep the level from previous cycle except for suspending on last data. Refere to "2. Functional Description * WAIT Output Function" in "s 128M FCRAM CHARACTERISTICS for MCP" for the details. *16 : WAIT output is driven in High level during write operation. 10
ACC
X X
ADV
WE
UB
OE
LB
MB84SF6H6H6L2-70
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET, ACC *1 *2 VCCr Supply *1 VCCf_1/ VCCf_2 / VCCQr Supply *1 ACC *1,*3 Symbol Tstg TA VIN, VOUT VCCr VCCf_1, VCCf_2, VCCQr VACC Rating Min -55 -30 -0.3 -0.3 -0.3 -0.5 Max +125 +85 VCCf_1 +0.3 VCCf_2 +0.3 VCCQr +0.3 +3.6 +2.5 +10.5 Unit C C V V V V V V
*1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to -1.0 V for periods of up to 10 ns. Maximum DC voltage on input or I/O pins is VCCf_1 + 0.3 V or VCCf_2 +0.3V or VCCQr + 0.2 V . During voltage transitions, input or I/O pins may overshoot to VCCf + 1.0 V or VCCf_2 + 1.0 V or VCCQr + 1.0 V for periods of up to 5 ns. *3 : Minimum DC input voltage on ACC pin is -0.5 V. During voltage transitions, ACC pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature VCCr Supply Voltages VCCf/VCCQr Supply Voltages Symbol TA VCCr VCCf_1, VCCf_2, VCCQr Value Min -30 +2.5 +1.65 Max +85 +3.1 +1.95 Unit C V V
Note : Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
11
MB84SF6H6H6L2-70
s ELECTRICAL CHARACTERISTICS
* DC Characteristics Parameter Input Leakage Current Output Leakage Current Flash VCCf Current (Standby) (Flash_1 & Flash_2) Flash_1 & 2 VCCf Current (Standby, Reset) (Flash_1 & Flash_2) Flash_1 & 2 VCCf Current (Automatic Sleep Mode)*3 (Flash_1 & Flash_2) Flash VCCf Active Burst Read Current (Flash_1 or Flash_2) Flash VCCf Active Asynchronous Read Current*1 (Flash_1 or Flash_2) Flash VCCf Active Current *2 (Flash_1 or Flash_2) Flash VCCf Active Current (Read-While-Program ) *4 (Flash_1 or Flash_2) Flash VCCf Active Current (Read-While-Erase) *4 (Flash_1 or Flash_2) FCRAM VCCr Power Down Current*5 Symbol ILI ILO ISB1f ISB2f ISB3f ICC1f Conditions VIN = VSS to VCCf, VCCQr VOUT = VSS to VCCf, VCCQr CEf = RESET = VCCf 0.2 V *9 RESET = VSS 0.2 V, CLK = VIL *9 VCCf = VCCf Max, CEf = VSS 0.2 V, RESET = VCCf 0.2 V, VIN = VCCf 0.2 V or VSS 0.2 V *9 CEf = VIL, OE = VIH, WE = VIH, 66 MHz *9 10 MHz ICC2f CEf = VIL, OE = VIH, WE = VIH *9 5 MHz ICC3f ICC4f ICC5f IDDPSr IDDP8r CEf = VIL, OE = VIH, VPP = VIH *9 CEf = VIL, OE = VIH *9 CEf = VIL, OE = VIH *9 -- -- -- -- -- -- -- 10 15 25 25 -- -- -- 15 40 60 60 10 120 150 mA mA mA A A A Min -1.0 -1.0 -- -- -- -- Value Typ Max -- +1.0 -- +1.0 1*7 1*7 1*7 15 20 50*7 50*7 50*7 30 30 mA Unit A A A A A mA
FCRAM VCCr Standby Current*5, *8
VCCr = VCCr Max, Sleep VCCQr = VCCQr Max, 16M Partial VIN = VIH or VIL, IDDP16r 32M Partial CE2r 0.2 V VCCr = VCCr Max, VCCQr = VCCQr Max, ISBSr VIN (including CLK) = VIH or VIL , CE1r = CE2r = VIH VCCr = VCCr Max, VCCQr = VCCQr Max, ISB1r VIN (including CLK) 0.2 V or VIN (including CLK) VCCQr - 0.2 V, CE1r = CE2r VCCQr - 0.2 V VCCQr = VCCQr Max, tCK = Min, ISB2r VIN 0.2 V or VIN VCCQr - 0.2 V, CE1r = CE2r VCCQr - 0.2 V
--
--
1.5
mA
--
--
300
A
--
--
350
A
(Continued)
12
MB84SF6H6H6L2-70
(Continued)
Parameter Symbol ICC1r FCRAM VCCr Active Current *5, *8 ICC2r Conditions VCCr = VCCr Max, tRC / tWC = Min VCCQr = VCCQr Max, VIN = VIH or VIL, CE1r = VIL and CE2r = VIH, tRC / tWC = 1 s IOUT = 0 mA VCCr = VCCr Max, VCCQr = VCCQr Max, VIN = VIH or VIL, CE1r = VIL and CE2r = VIH, IOUT= 0 mA, tPRC = Min VCCr = VCCr Max, VCCQr = VCCQr Max, VIN = VIH or VIL, CE1r = VIL and CE2r = VIH, tCK = tCK Min, BL = Continuous, IOUT = 0 mA -- -- IOL = 0.1 mA IOL = 1.0 mA IOH = - 0.1 mA VCCQr = VCCQr Min, IOH = - 0.5 mA -- Flash_1 or Flash_2 FCRAM Flash_1 or Flash_2 FCRAM Min -- -- Value Typ Max -- -- 35 5 Unit mA mA
FCRAM VCCr Page Read Current *5, *8
ICC3r
--
--
15
mA
FCRAM VCCr Burst Access Current *5, *8 Input Low Level Input High Level Output Low Voltage Level
ICC4r
--
--
30 VCC x 0.2 *6 VCC + 0.2 *6 0.1 0.4 -- -- 9.5
mA
VIL VIH VOLf VOLr VOHf
-0.3 VCC - 0.4 *6 -- -- VCCf - 0.1 1.4 8.5
-- -- -- -- -- -- --
V V V V V V V
Output High Voltage Level VOHr Voltage for ACC Program Acceleration*10 VACC
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component. *2 : ICC active while Embedded Algorithm (program or erase) is in progress. *3 : Automatic sleep mode enables the low power mode when address remains stable for tACC + 60 ns. *4 : Embedded Alogorithm (program or erase) is in progress. (@5 MHz) *5 : FCRAM DC Current is measured after following POWER-UP timing. *6 : VCC means VCCf_1 or VCCf_2 or VCCQr. *7 : Actual Standby Current is twice of what is indicated in the table, due to two Flash chips embedment withn one device. *8 : IOUT depemds on the output load comditions. *9 : CEf means CEf_1 or CEf_2. *10 : Applicable for only VCCf_1 or VCCf_2.
13
MB84SF6H6H6L2-70
* AC Characteristics * CE Timing Parameter CE Recover Time CEf Hold Time CE1r High to WE Invalid time for Standby Entry Symbol JEDEC -- -- -- Standard tCCR tCHOLD tCHWX Condition -- -- -- Value Min 0 3 10 Max -- -- -- Unit ns ns ns
* Timing Diagram for alternating RAM to Flash
CEf_1 or CEf_2
tCCR
tCCR
CE1r
WE
tCHWX tCHOLD
tCCR
tCCR
CE2r
* NOR Flash_1&2 Characteristics Please refer to "s 128M BURST FLASH MEMORY CARACTERISTICS for MCP". * FCRAM Characteristics Please refer to "s 128M FCRAM CHARACTERISTICS for MCP".
14
MB84SF6H6H6L2-70
s 128M BURST FLASH MEMORY CHARACTERISTICS for MCP
1. Flexible Sector-erase Architecture on Flash Memory * Sixteen 4K words, and one hundred twenty-six 32K words. * Individual-sector, multiple-sector, or bulk-erase capability.
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 : 8KB : 8KB : 8KB : 8KB : 8KB : 8KB : 8KB : 8KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 1FFFFFh SA71 : 64KB SA72 : 64KB SA73 : 64KB SA74 : 64KB SA75 : 64KB SA76 : 64KB SA77 : 64KB SA78 : 64KB SA79 : 64KB SA80 : 64KB SA81 : 64KB SA82 : 64KB SA83 : 64KB SA84 : 64KB SA85 : 64KB SA86 : 64KB SA87 : 64KB SA88 : 64KB SA89 : 64KB SA90 : 64KB SA91 : 64KB SA92 : 64KB SA93 : 64KB SA94 : 64KB SA95 : 64KB SA96 : 64KB SA97 : 64KB SA98 : 64KB SA99 : 64KB SA100: 64KB SA101: 64KB SA102: 64KB SA103: 64KB SA104: 64KB SA105: 64KB SA106: 64KB SA107: 64KB SA108: 64KB SA109: 64KB SA110: 64KB SA111: 64KB SA112: 64KB SA113: 64KB SA114: 64KB SA115: 64KB SA116: 64KB SA117: 64KB SA118: 64KB SA119: 64KB SA120: 64KB SA121: 64KB SA122: 64KB SA123: 64KB SA124: 64KB SA125: 64KB SA126: 64KB SA127: 64KB SA128: 64KB SA129: 64KB SA130: 64KB SA131: 64KB SA132: 64KB SA133: 64KB SA134: 64KB 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3FFFFFh SA135: 64KB SA136: 64KB SA137: 64KB SA138: 64KB SA139: 64KB SA140: 64KB SA141: 64KB SA142: 64KB SA143: 64KB SA144: 64KB SA145: 64KB SA146: 64KB SA147: 64KB SA148: 64KB SA149: 64KB SA150: 64KB SA151: 64KB SA152: 64KB SA153: 64KB SA154: 64KB SA155: 64KB SA156: 64KB SA157: 64KB SA158: 64KB SA159: 64KB SA160: 64KB SA161: 64KB SA162: 64KB SA163: 64KB SA164: 64KB SA165: 64KB SA166: 64KB SA167: 64KB SA168: 64KB SA169: 64KB SA170: 64KB SA171: 64KB SA172: 64KB SA173: 64KB SA174: 64KB SA175: 64KB SA176: 64KB SA177: 64KB SA178: 64KB SA179: 64KB SA170: 64KB SA181: 64KB SA182: 64KB SA183: 64KB SA184: 64KB SA185: 64KB SA186: 64KB SA187: 64KB SA188: 64KB SA189: 64KB SA190: 64KB SA191: 64KB SA192: 64KB SA193: 64KB SA194: 64KB SA195: 64KB SA196: 64KB SA197: 64KB SA198: 64KB 400000h 408000h 410000h 418000h 420000h 428000h 430000h 438000h 440000h 448000h 450000h 458000h 460000h 468000h 470000h 478000h 480000h 488000h 490000h 498000h 4A0000h 4A8000h 4B0000h 4B8000h 4C0000h 4C8000h 4D0000h 4D8000h 4E0000h 4E8000h 4F0000h 4F8000h 500000h 508000h 510000h 518000h 520000h 528000h 530000h 538000h 540000h 548000h 550000h 558000h 560000h 568000h 570000h 578000h 580000h 588000h 590000h 598000h 5A0000h 5A8000h 5B0000h 5B8000h 5C0000h 5C8000h 5D0000h 5D8000h 5E0000h 5E8000h 5F0000h 5F8000h 5FFFFFh SA199: 64KB SA200: 64KB SA201: 64KB SA202: 64KB SA203: 64KB SA204: 64KB SA205: 64KB SA206: 64KB SA207: 64KB SA208: 64KB SA209: 64KB SA210: 64KB SA211: 64KB SA212: 64KB SA213: 64KB SA214: 64KB SA215: 64KB SA216: 64KB SA217: 64KB SA218: 64KB SA219: 64KB SA220: 64KB SA221: 64KB SA222: 64KB SA223: 64KB SA224: 64KB SA225: 64KB SA226: 64KB SA227: 64KB SA228: 64KB SA229: 64KB SA230: 64KB SA231: 64KB SA232: 64KB SA233: 64KB SA234: 64KB SA235: 64KB SA236: 64KB SA237: 64KB SA238: 64KB SA239: 64KB SA240: 64KB SA241: 64KB SA242: 64KB SA243: 64KB SA244: 64KB SA245: 64KB SA246: 64KB SA247: 64KB SA248: 64KB SA249: 64KB SA250: 64KB SA251: 64KB SA252: 64KB SA253: 64KB SA254: 64KB SA255: 64KB SA256: 64KB SA257: 64KB SA258: 64KB SA259: 64KB SA260: 64KB SA261: 64KB SA262: 8KB SA263: 8KB SA264: 8KB SA265: 8KB SA266: 8KB SA267: 8KB SA268: 8KB SA269: 8KB 600000h 608000h 610000h 618000h 620000h 628000h 630000h 638000h 640000h 648000h 650000h 658000h 660000h 668000h 670000h 678000h 680000h 688000h 690000h 698000h 6A0000h 6A8000h 6B0000h 6B8000h 6C0000h 6C8000h 6D0000h 6D8000h 6E0000h 6E8000h 6F0000h 6F8000h 700000h 708000h 710000h 718000h 720000h 728000h 730000h 738000h 740000h 748000h 750000h 758000h 760000h 768000h 770000h 778000h 780000h 788000h 790000h 798000h 7A0000h 7A8000h 7B0000h 7B8000h 7C0000h 7C8000h 7D0000h 7D8000h 7E0000h 7E8000h 7F0000h 7F8000h 7F9000h 7FA000h 7FB000h 7FC000h 7FD000h 7FE000h 7FF000h 7FFFFFh
BANK A
BANK C
BANK B
BANK B
Sector Architecture 15
BANK D
BANK C
MB84SF6H6H6L2-70
* FlexBankTM Architecture Bank 1 Bank Splits Volume Combination 1 2 3 4 16 Mbit 48 Mbit 48 Mbit 16 Mbit Bank A Bank B Bank C Bank D
Bank 2 Volume 112Mbit 96 Mbit 96 Mbit 112Mbit Combination Remember (Bank B, C, D) Remember (Bank A, C, D) Remember (Bank A, B, D) Remember (Bank A, B, C)
* Simultaneous Operation Case 1 2 3 4 5 6 7
Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode
Bank 2 Status Read mode Autoselect mode Program mode Erase mode Read mode Read mode Read mode
Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) meant to specify each of the Banks.
16
MB84SF6H6H6L2-70
* Sector Address Tables (Bank A) Sector Address Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Bank Address A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 0 0 0 00000000 0 0 0 00000001 0 0 0 00000010 0 0 0 00000011 0 0 0 00000100 0 0 0 00000101 0 0 0 00000110 0 0 0 00000111 0 0 0 00001XXX 0 0 0 00010XXX 0 0 0 00011XXX 0 0 0 00100XXX 0 0 0 00101XXX 0 0 0 00110XXX 0 0 0 00111XXX 0 0 0 01000XXX 0 0 0 01001XXX 0 0 0 01010XXX 0 0 0 01011XXX 0 0 0 01100XXX 0 0 0 01101XXX 0 0 0 01110XXX 0 0 0 01111XXX 0 0 0 10000XXX 0 0 0 10001XXX 0 0 0 10010XXX 0 0 0 10011XXX 0 0 0 10100XXX 0 0 0 10101XXX 0 0 0 10110XXX 0 0 0 10111XXX 0 0 0 11000XXX 0 0 0 11001XXX 0 0 0 11010XXX 0 0 0 11011XXX 0 0 0 11100XXX 0 0 0 11101XXX 0 0 0 11110XXX 0 0 0 11111XXX Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 06FFFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh
Bank A
17
MB84SF6H6H6L2-70
* Sector Address Tables (Bank B) Sector Address Bank Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 Bank Address A22 A21 A20 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh
Bank B
(Continued)
18
MB84SF6H6H6L2-70
Sector Address Bank Sector SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 Bank Address A22 A21 A20 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 A19 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A18 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 A17 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 A16 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
(x 16) Address Range 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh 2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh (Continued)
Bank B
19
MB84SF6H6H6L2-70
(Continued)
Sector Address Bank Sector SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Bank Address A22 A21 A20 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 A19 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 370000h to 377FFFh 378000h to 37FFFFh 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3FFFFFh
Bank B
20
MB84SF6H6H6L2-70
* Sector Address Tables (Bank C) Sector Address Bank Sector SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 Bank Address A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 1 0 0 00000XXX 1 0 0 00001XXX 1 0 0 00010XXX 1 0 0 00011XXX 1 0 0 00100XXX 1 0 0 00101XXX 1 0 0 00110XXX 1 0 0 00111XXX 1 0 0 01000XXX 1 0 0 01001XXX 1 0 0 01010XXX 1 0 0 01011XXX 1 0 0 01100XXX 1 0 0 01101XXX 1 0 0 01110XXX 1 0 0 01111XXX 1 0 0 10000XXX 1 0 0 10001XXX 1 0 0 10010XXX 1 0 0 10011XXX 1 0 0 10100XXX 1 0 0 10101XXX 1 0 0 10110XXX 1 0 0 10111XXX 1 0 0 11000XXX 1 0 0 11001XXX 1 0 0 11010XXX 1 0 0 11011XXX 1 0 0 11100XXX 1 0 0 11101XXX 1 0 0 11110XXX 1 0 0 11111XXX 1 0 1 00000XXX 1 0 1 00001XXX 1 0 1 00010XXX 1 0 1 00011XXX 1 0 1 00100XXX 1 0 1 00101XXX 1 0 1 00110XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 400000h to 407FFFh 408000h to 40FFFFh 410000h to 417FFFh 418000h to 41FFFFh 420000h to 427FFFh 428000h to 42FFFFh 430000h to 437FFFh 438000h to 43FFFFh 440000h to 447FFFh 448000h to 44FFFFh 450000h to 457FFFh 458000h to 45FFFFh 460000h to 467FFFh 468000h to 46FFFFh 470000h to 477FFFh 478000h to 47FFFFh 480000h to 487FFFh 488000h to 48FFFFh 490000h to 497FFFh 498000h to 49FFFFh 4A0000h to 4A7FFFh 4A8000h to 4AFFFFh 4B0000h to 4B7FFFh 4B8000h to 4BFFFFh 4C0000h to 4C7FFFh 4C8000h to 4CFFFFh 4D0000h to 4D7FFFh 4D8000h to 4DFFFFh 4E0000h to 4E7FFFh 4E8000h to 4EFFFFh 4F0000h to 4F7FFFh 4F8000h to 4FFFFFh 500000h to 507FFFh 508000h to 50FFFFh 510000h to 517FFFh 518000h to 51FFFFh 520000h to 527FFFh 528000h to 52FFFFh 530000h to 537FFFh
Bank C
(Continued)
21
MB84SF6H6H6L2-70
Sector Address Bank Sector SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 Bank Address A22 A21 A20 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 A19 A18 A17 A16 A15 A14 A13 A12 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX 01110XXX 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 11111XXX 00000XXX 00001XXX 00010XXX 00011XXX 00100XXX 00101XXX 00110XXX 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX
Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
(x 16) Address Range 538000h to 53FFFFh 540000h to 547FFFh 548000h to 54FFFFh 550000h to 557FFFh 558000h to 55FFFFh 560000h to 567FFFh 568000h to 56FFFFh 570000h to 577FFFh 578000h to 57FFFFh 580000h to 587FFFh 588000h to 58FFFFh 590000h to 597FFFh 598000h to 59FFFFh 5A0000h to 5A7FFFh 5A8000h to 5AFFFFh 5B0000h to 5B7FFFh 5B8000h to 5BFFFFh 5C0000h to 5C7FFFh 5C8000h to 5CFFFFh 6D0000h to 5D7FFFh 6D8000h to 5DFFFFh 5E0000h to 5E7FFFh 5E8000h to 5EFFFFh 5F0000h to 5F7FFFh 5F8000h to 5FFFFFh 600000h to 607FFFh 608000h to 60FFFFh 610000h to 617FFFh 618000h to 61FFFFh 620000h to 627FFFh 628000h to 62FFFFh 630000h to 637FFFh 638000h to 63FFFFh 640000h to 647FFFh 648000h to 64FFFFh 650000h to 657FFFh 658000h to 65FFFFh 660000h to 667FFFh 668000h to 66FFFFh (Continued)
Bank C
22
MB84SF6H6H6L2-70
(Continued)
Sector Address Bank Sector SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 Bank Address A22 A21 A20 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 A19 A18 A17 A16 A15 A14 A13 A12 01110XXX 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 11111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 670000h to 677FFFh 678000h to 67FFFFh 680000h to 687FFFh 688000h to 68FFFFh 690000h to 697FFFh 698000h to 69FFFFh 6A0000h to 6A7FFFh 6A8000h to 6AFFFFh 6B0000h to 6B7FFFh 8B8000h to 6BFFFFh 6C0000h to 6C7FFFh 6C8000h to 6CFFFFh 6D0000h to 6D7FFFh 6D8000h to 6DFFFFh 6E0000h to 6E7FFFh 6E8000h to 6EFFFFh 6F0000h to 6F7FFFh 6F8000h to 6FFFFFh
Bank C
23
MB84SF6H6H6L2-70
* Sector Address Tables (Bank D) Sector Address Bank Sector SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 Bank Address A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 1 1 1 00000XXX 1 1 1 00001XXX 1 1 1 00010XXX 1 1 1 00011XXX 1 1 1 00100XXX 1 1 1 00101XXX 1 1 1 00110XXX 1 1 1 00111XXX 1 1 1 01000XXX 1 1 1 01001XXX 1 1 1 01010XXX 1 1 1 01011XXX 1 1 1 01100XXX 1 1 1 01101XXX 1 1 1 01110XXX 1 1 1 01111XXX 1 1 1 10000XXX 1 1 1 10001XXX 1 1 1 10010XXX 1 1 1 10011XXX 1 1 1 10100XXX 1 1 1 10101XXX 1 1 1 10110XXX 1 1 1 10111XXX 1 1 1 11000XXX 1 1 1 11001XXX 1 1 1 11010XXX 1 1 1 11011XXX 1 1 1 11100XXX 1 1 1 11101XXX 1 1 1 11110XXX 1 1 1 11111000 1 1 1 11111001 1 1 1 11111010 1 1 1 11111011 1 1 1 11111100 1 1 1 11111101 1 1 1 11111110 1 1 1 11111111 Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 (x 16) Address Range 700000h to 707FFFh 708000h to 70FFFFh 710000h to 717FFFh 718000h to 71FFFFh 720000h to 727FFFh 728000h to 72FFFFh 730000h to 737FFFh 738000h to 73FFFFh 740000h to 747FFFh 748000h to 74FFFFh 750000h to 757FFFh 758000h to 75FFFFh 760000h to 767FFFh 768000h to 76FFFFh 770000h to 777FFFh 778000h to 77FFFFh 780000h to 787FFFh 788000h to 78FFFFh 790000h to 797FFFh 798000h to 79FFFFh 7A0000h to 7A7FFFh 7A8000h to 7AFFFFh 7B0000h to 7B7FFFh 7B8000h to 7BFFFFh 7C0000h to 7C7FFFh 7C8000h to 7CFFFFh 7D0000h to 7D7FFFh 7D8000h to 7DFFFFh 7E0000h to 7E7FFFh 7E8000h to 7EFFFFh 7F0000h to 7F7FFFh 7F8000h to 7F8FFFh 7F9000h to 7F9FFFh 7FA000h to 7FAFFFh 7FB000h to 7FBFFFh 7FC000h to 7FCFFFh 7FD000h to 7FDFFFh 7FE000h to 7FEFFFh 7FF000h to 7FFFFFh
Bank D
24
MB84SF6H6H6L2-70
* Sector Group Address Table Sector Group A22 A21 A20 SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
A18 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
A17 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X X X X
A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X
A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X
A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X
A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X
Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78
(Continued)
25
MB84SF6H6H6L2-70
Sector Group SGA28 SGA29 SGA30 SGA31 SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 SGA48 SGA49 SGA50 SGA51
A22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
A20 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1
A19 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
A18 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A16 X X X X X X X X X X X X X X X X X X X X X X X X
A15 X X X X X X X X X X X X X X X X X X X X X X X X
A14 X X X X X X X X X X X X X X X X X X X X X X X X
A13 X X X X X X X X X X X X X X X X X X X X X X X X
A12 X X X X X X X X X X X X X X X X X X X X X X X X
Sectors SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA134 SA135 to SA138 SA139 to SA142 SA143 to SA146 SA147 to SA150 SA151 to SA154 SA155 to SA158 SA159 to SA162 SA163 to SA166 SA167 to SA170 SA171 to SA174
(Continued)
26
MB84SF6H6H6L2-70
(Continued) Sector Group
SGA52 SGA53 SGA54 SGA55 SGA56 SGA57 SGA58 SGA59 SGA60 SGA61 SGA62 SGA63 SGA64 SGA65 SGA66 SGA67 SGA68 SGA69 SGA70 SGA71 SGA72 SGA73 SGA74 SGA75 SGA76 SGA77 SGA78 SGA79 SGA80 SGA81 SGA82 SGA83
A22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A21 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A20 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A19 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A18 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1
A16 X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1
A15 X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1
A14 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1
A13 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1
A12 X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1
Sectors SA175 to SA178 SA179 to SA182 SA183 to SA186 SA187 to SA190 SA191 to SA194 SA195 to SA198 SA199 to SA202 SA203 to SA206 SA207 to SA210 SA211 to SA214 SA215 to SA218 SA219 to SA222 SA223 to SA226 SA227 to SA230 SA231 to SA234 SA235 to SA238 SA239 to SA242 SA243 to SA246 SA247 to SA250 SA251 to SA254 SA255 to SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
27
MB84SF6H6H6L2-70
* Sector Protection Verify Autoselect Codes Table A7 A6 A5 A4 Type A22 to A12 Manufacture's Code Device Code Extended Device Code *2 BA BA BA BA Sector Group Addresses L L L L L L L L L L L L L L L L L L L L
A3 L L H H L
A2 L L H H L
A1 L L H H H
A0 L H L H L
Code (HEX) 04h 227Eh 2218h 2200h 01h*1 DQ7 - Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6 - Customer Lock Bit 1 = Locked, 0 = Not Locked
Sector Group Protection
Indicator Bits
BA
L
L
L
L
L
L
H
H
Legend : L = VIL, H = VIH. See DC Characteristics for voltage levels. *1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.
28
MB84SF6H6H6L2-70
* Flash Memory Command Definitions
Command Sequence Bus First Bus Second Write Third Write FourthWrite Fifth Write Sixth Write Seventh Write Write Cycle Cycle Cycle Cycle Cycle Cycle Write Cycle Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Req'd
Read / Reset Read / Reset Autoselect Program Chip Erase Sector Erase Erase Suspend Erase Resume Set to Fast Mode Fast Program Reset from Fast Mode *1 Set Burst Mode Configuration Register Query HiddenROM Entry HiddenROM Program*3 HiddenROM Exit*3 HiddenROM Protect*3
1 3 3 4 6 6 1 1 3 2 2 3 1 3
XXXh F0h
RA
RD 55h 55h 55h 55h 55h -- -- 55h PD
--
--
-- RA -- PA 555h 555h -- -- --
-- RD -- PD
-- -- -- --
-- -- -- -- 55h 55h -- -- --
-- -- -- -- 555h SA -- -- --
-- -- -- -- 10h 30h -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- --
555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh BA BA XXXh BA B0h 30h A0 -- -- PA
555h F0h (BA) 90h 555h 555h A0h 555h 80h 555h 80h -- -- -- --
AAh 2AAh AAh 2AAh -- -- -- -- -- --
555h AAh 2AAh
555h 20h
90h XXXh F0h*2 55h --
--
--
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
555h AAh 2AAh (BA) 55h 98h --
(CR) C0h 555h -- --
555h AAh 2AAh 55h 555h 88h
4
555h AAh 2AAh 55h 555h A0h
(HRA) PD PA
--
--
--
--
--
--
4
555h AAh 2AAh 55h 555h 90h XXXh 00h
--
--
--
--
--
--
6
555h AAh 2AAh 55h 555h 60h OPBP 68h OPBP 48h XXXh RD(0)
--
--
Legend : RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the ADV pulse or active edge of CLK while ADV = VIL whichever comes first or falling edge of wirte pulse while ADV = VIL. SA = Address of the sector to be erased. The combination of A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address. Address setted by A22, A21, A20 will select Bank A, Bank B, Bank C and Bank D. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of write pulse. SGA = Sector group address to be protected. HRA = Address of the HiddenROM area 000000h to 00007Fh HRBA = Bank Address of the HiddenROM area (A22 = A21 = A20 = A19 = A18 = VIL) (Continued) 29
MB84SF6H6H6L2-70
(Continued) RD (0) = Read Data bit. If programmed, DQ0 = 1, if erase, DQ0 = 0 OPBP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 1, 0, 1, 0) CR = Configuration Register address bits A19 to A12.
*1: This command is valid during Fast Mode. *2: This command is valid during HiddenROM mode. *3: The data "00h" is also acceptable. Notes : * Address bits A22 to A11 = X = "H" or "L" for all address commands except for PA, SA, BA, SGA, OPBP . * Bus operations are defined in "s DEVICE BUS OPERATIONS". * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
30
MB84SF6H6H6L2-70
2. AC Characteristics * Synchronous/Burst Read Symbol Parameter JEDEC Latency Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK*1 Address Hold Time from CLK*2 Data Hold Time from Next Clock Cycle Chip Enable to RY/BY Valid Output Enable to Output Valid Chip Enable to High-Z Output Enable to High-Z CEf Setup Time to CLK Ready Access Time from CLK CEf Setup Time to ADV ADV Set Up Time to CLK ADV Hold Time to CLK CLK to access resume CLK to High-Z Output Enable Setup Time Read Cycle for Continuous suspend Read Cycle Time -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Standard tIACC tBACC tACS tACH tBDH tCR tOE tCEZ tOEZ tCES tRACC tCAS tAVSC tAVHC tCKA tCKZ tOES tRCC tRC Min -- -- 4 6 3 -- -- -- -- 4 -- 0 4 6 -- -- 4 -- 56 Max 71 11 -- -- -- 11 11 8 8 -- 11 -- -- -- 11 8 -- 1 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns Value Unit
*1 : Access Time is from the last of either stable addresses . *2 : Addresses are latched on the active edge of CLK. Note : Test Conditions Output Load : VCCQr =1.65 V to 1.95 V : 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to VCCf Timing measurement reference level : Input : 0.5 x VCCf, Output : 0.5 x VCCf
31
MB84SF6H6H6L2-70
* Asynchronous Read Symbol Parameter JEDEC Standard Read Cycle Time Access Time from CEf Low Asynchronous Access Time* Output Enable to Output Valid Read Output Enable Hold Time Toggle and Data Polling Chip Enable to High-Z CEf High During Toggle Bit Polling Output Enable to High-Z -- -- -- tCEZ tCEPH tOEZ -- tOEH 8 -- 20 -- -- 8 -- 8 ns ns ns ns -- -- -- -- tRC tCE tACC tOE Min 56 -- -- -- 0 Max -- 56 56 11 -- ns ns ns ns ns Value Unit
* : Asynchronous Access Time is from the last of either stable addresses or the falling edge of ADV.
* Hardware Reset (RESET) Symbol Parameter JEDEC RESET Pin Low (During Embedded Algorithms) to Read Mode *1 RESET Pulse Width Reset High Time Before Read *2 Power On/Off Time -- -- -- -- Standard tREADY tRP tRH tPS Min -- 500 200 0 Max 20 -- -- -- s ns ns ns Value Unit
*1 : Access Time is from the last of either stable addresses. *2 : Addresses are latched on the active edge of CLK. Note : Test Conditions : Output Load : VCCQr =1.65 V to 1.95 V : 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to VCCf Timing measurement reference level : Input : 0.5 x VCCf, Output : 0.5 x VCCf
32
MB84SF6H6H6L2-70
* Write (Erase/Program) Operations Parameter Write Cycle Time Address Setup Time Address Hold Time ADV Low Time CEf Low to ADV High Data Setup Time Data Hold Time Read Recovery Time Before Write CEf Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation* VCCf Setup Time CEf Setup Time to WE ADV Set Up Time to CLK ADV Hold Time to CLK ADV Setup Time to WE ADV Hold Time to WE Address Setup Time to CLK Address Hold Time to CLK Address Setup Time to ADV Address Hold Time to ADV WE Low to CLK ADV High to WE Low CLK to WE Low Erase Time-out TIme *1 : Not 100% tested. *2 : See the "Erase and Programming Performance" section in "BS12DH" datasheet for more information. Notes : * Does not include the preprogramming time. * Access Time is from the last of either stable addresses. * Addresses are latched on the active edge of CLK. -- -- -- --
1
Symbol JEDEC tAVAV tAVWL tWLAX -- -- tDVWH tWHDX tGHWL tWHEH tEHWH tWHWL -- tWHWH1 tWHWH2 -- tELWL -- -- -- -- -- -- -- Standard tWC tAS tAH tAVDP tCLAH tDS tDH tGHWL tCH tWP tWPH tSR/W tWHWH1 tWHWH2 tVCS tCS tAVSC tAVHC tAVSW tAVHW tACS tACH tAAS tAAH tWLC tAHWL tCWL tTOW Min 56 0 20 10 10 20 0 0 0 20 20 0 -- -- 50 0 4 6 4 6 4 6 4 6 0 5 5 50
Value Typ -- -- -- -- -- -- -- -- -- -- -- -- 6 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns ns ns ns ns ns ns ns ns ns ns s
Sector Erase Operation* *
1, 2
33
MB84SF6H6H6L2-70
* Erase and Programming Performance Value Parameter Min Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle -- -- -- 100,000 Typ 0.5 6.0 50.3 -- Max 2 100 200 -- s s s cycle Excludes programming prior to erasure Excludes system level overhead Excludes system level overhead -- Unit Remarks
Notes : * Typical Erase Conditions : TA = +25C, VCCf = 1.8 V * Typical Program Conditions : TA = +25C, VCCf = 1.8 V, Data = checker * Test Conditions : Output Load : VCCQr =1.65 V to 1.95 V : 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to VCCf Timing measurement reference level : Input: 0.5 x VCCf, Output : 0.5 x VCCf
34
MB84SF6H6H6L2-70
* Synchronous Burst Mode Read (Latched By Rising Active CLK)
7 cycles for initial access shown. tCES tCEZ 2 3 4 5 6 7
CEf
1
CLK
tAVSC
ADV
tACS
tAVHC tBDH Aa tACH tBACC High-Z tIACC tACC tCKA tRACC High-Z Da Da + 1 Da + n
A22 to A0 DQ15 to DQ0 OE
tCR
tOES
RY/BY
High-Z
Notes : * Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. * The device is in synchronous mode.
35
MB84SF6H6H6L2-70
* Synchronous Burst Mode Read (Latched By Falling Active CLK)
4 cycles for initial access shown. tCES tCEZ
CEf
1 2 3 4 5
CLK
tAVSC
ADV
tAVHC tACS tBDH Aa tACH tBACC High-Z tIACC tACC tOES Da Da + 1 Da + n
A22 to A0
DQ15 to DQ0
OE
tCR High-Z
tCKA tRACC High-Z
RY/BY
Notes : * Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active falling edge. * The device is in synchronous mode.
36
MB84SF6H6H6L2-70
* 8-word Linear Burst
tCES 1 2
CEf CLK
tAVSC
7 cycles for initial access shown.
3 4 5 6 7
ADV
tACS
tAVHC tBDH Aa tACH tBACC tIACC tACC tCKA tRACC D0 D1 D2 D3 D4 D5 D6 D7 tCEZ
A22 to A0 DQ15 to DQ0
OE RY/BY
High-Z
tOES tCR
Note : Figure assumes 7 wait states for initial access, synchronous read. D0 to D7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. See "Requirements for Synchronous (Burst) Read Operation". The Set Configuration Register command sequence has been written with A18 = 1; device will output RY/BY with valid data.
37
MB84SF6H6H6L2-70
* 8-word Linear Burst with Wrap Around
tCES 1 2
7 cycles for initial access shown.
3 4 5 6 7
CEf CLK
tAVSC
ADV
tACS
tAVHC tBDH Aa tACH tBACC tIACC tACC tCKA tRACC D6 D7 D0 D1 D2 D3 D4 D5 tCEZ
A22 to A0 DQ15 to DQ0
OE RY/BY
High-Z
tOES tCR
Note : Figure assumes 7 wait states for initial access, synchronous read. D0 to D7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in range (A6). See "Requirements for Synchronous (Burst) Read Operation". The Set Configuration Register command sequence has been written with A18 = 1; device will output RY/BY with valid data.
38
MB84SF6H6H6L2-70
* Linear Burst with RY/BY Set One Cycle Before Data
6 wait cycles for initial access shown.
CEf CLK
tAVSC
tCES 1 2 3 4 5 6
tCEZ
ADV
tACS
tAVHC tBDH Aa tACH tBACC High-Z tIACC tOES tACC tCKA D0 tRACC High-Z D1 D2 D3 Da + n
A22 to A0 DQ15 to DQ0
OE
tCR
RY/BY
High-Z
Note : Figure assumes 6 wait states for initial access, 66 MHz clock, and synchronous read. The Set Configuration Register command sequence has been written with A18 = 0; device will output RY/BY one cycle before valid data.
39
MB84SF6H6H6L2-70
* Burst Suspend
Suspend CLK
VIH
Resume
ADV Address
tOES tOES
OE
tCKZ tCKA
Data
D20 tRACC tRACC
D20
D21
D22
D23
D24
D25
D26
RY/BY CEf
VIL
Note : The Set Configuration Register command sequence must be written with A18 =1; device will output RY/BY with valid data. The clock during Burst Suspend is "Don't care".
40
MB84SF6H6H6L2-70
* Burst Suspend prior to Initial Access
1
2
3
4
Suspend
5 6 7
Resume
CLK
ADV Address
A(n) tOES
OE
tCKA
Data
tRACC
D(n)
D(n+1)
D(n+2)
D(n+3)
D(n+4)
RY/BY CEf
Note : Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence must be written with A18 =1; device will output RY/BY with valid data. The clock during Burst Suspend is "Don't care".
41
MB84SF6H6H6L2-70
* Read Cycle for Continuous Suspend
1
2
3
4
Suspend
5 6 7
Resume
CLK
tRCC
ADV Address
A(n) tOES
OE
tCKA tRCC
Data
D(n)
Invalid Data
RY/BY
CEf
Notes : * Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence must be written with A18 =1; device will output RY/BY with valid data. The clock during Burst Suspend is "Don't care". * Burst plus Burst Suspend should not last longer than tRCC without relaching an address. After the period of tRCC the device will output invalid data.
42
MB84SF6H6H6L2-70
* Asynchronous Mode Read
tRC
Address
tACC
Address Stable
CEf
tOE tCEZ
OE
tOEZ tOEH
WE
tCE High-Z tOH High-Z
Outputs
Outputs Valid
Notes : * ADV is assumed to be VIL. * Configuration Register is set to Asynchronous mode.
43
MB84SF6H6H6L2-70
* Reset Timings
CEf, OE
tRH
RESET
tRP
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
CEf, OE
tREADY
RESET
tRP
* Power On/Off Timings (128M Burst Flash)
tPS
tPS
RESET
VCCf 0V
1.65 V
1.65 V
Address
Valid Data In
Data
Valid Data Out
tRH tACC
44
MB84SF6H6H6L2-70
* Program Operation Timings at Asynchronous Mode (WE latch)
Program Command Sequence (last two cycles)
Read Status Data
CLK
tAVSW tAVHW
ADV VIL
3rd Bus Cycle Data Polling PA tAH PA VA tRC tOH
Address
555h tWC tAS tDS tDH
Data
A0h
PD
DQ7
DOUT tCEZ
DOUT
CEf
tCS tCH tOEZ tCE
OE
tGHWL tWP tWPH tOE tWHWH1
WE
Notes : * PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. * "In progress" and "complete" refer to status of program operation. * A22 to A12 are don't care during command sequence unlock cycles. * CLK is "Don't care". * Configuration Register is set to Asynchronous mode.
45
MB84SF6H6H6L2-70
* Program Operation Timings at Asynchronous Mode (ADV latch)
Program Command Sequence (last two cycles)
Read Status Data
CLK
tCLAH
ADV
tAAH tAAS
tAVDP
Address Data
555h
PA
VA In Progress
VA
A0h tDS tDH
PD
Complete
CEf
OE WE
tCH tAHWL tWP tWHWH1 tWPH tWC tVCS
tCS
VCCf
Notes : * * * * * *
PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. "In progress" and "complete" refer to status of program operation. A22 to A12 are don't care during command sequence unlock cycles. CLK is "Don't care". Configuration Register is set to Asynchronous mode. Addresses are latched on the rising edge of ADV.
46
MB84SF6H6H6L2-70
* Program Operation Timings at Synchronous Mode (WE latch)
Program Command Sequence (last two cycles) Read Status Data
CLK
tAVSW
tAVHW
ADV
Address Data
555h tAS tAH A0h
PA
VA In Progress tDH
VA
PD tDS
Complete
CEf
OE WE
tWLC tWP
tCH
tWPH tCS tWC
tWHWH1
tVCS
VCCf
Notes : * * * * *
PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. "In progress" and "complete" refer to status of program operation. A22 to A12 are "don't care" during command sequence unlock cycles. Configuration Register is set to Synchronous mode. Addresses are latched on the first of either the falling edge of WE or active edge of CLK. When "tWLC" is not met then ADV/address set up and hold time to CLK will be required.
47
MB84SF6H6H6L2-70
* Program Operation Timings at Synchronous Mode (CLK latch)
Program Command Sequence (last two cycles)
Read Status Data
CLK
tACS tACH tAVSC tAVHC
CEf
ADV
Address Data
tCAS
555h
PA
VA In Progress
VA
A0h tDS tDH
PD
Complete
OE WE
tCWL tWP
tCH
tWHWH1 tVCS tWPH tWC
Vccf
Notes : * * * * *
PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. "In progress" and "complete" refer to status of program operation. A22 to A12 are don't care during command sequence unlock cycles. Configuration Register is set to Synchronous mode. Addresses are latched on the first of either the active edge of CLK or the rising edge of ADV.
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MB84SF6H6H6L2-70
* Chip/Sector Erase Command Sequence
Program Command Sequence (last two cycles)
Read Status Data
CLK
tAVSW tAVHW
ADV
Address Data
2AAh tAS tAH 55h
SA 555h for chip erase
VA 10h for chip erase 30h tDS tDH In Progress
VA
Complete
tAVHC
CEf
OE WE
tWLC tWP
tCH
tWPH tCS tWC
tWHWH2
tVCS
VCCf
Notes : * SA is the sector address for Sector Erase. * Address bits A22 to A12 are don't cares during unlock cycles in the command sequence. * This timing is for Synchronous mode.
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MB84SF6H6H6L2-70
* Data Polling Timings/Toggle Bit Timings (During Embedded Algorithm)
ADV
tCE tCEZ
CEf
tCH tOE tOEZ
OE
tOEH
WE
tACC
Address
VA
VA
Status Data
Status Data
Notes : * Status reads in figure are shown as asynchronous mode. * VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data Polling will output true data and the toggle bits will stop toggling.
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MB84SF6H6H6L2-70
* Synchronous Data Polling Timings/Toggle Bit Timings
CEf CLK ADV Address OE
tIACC tIACC Status Data Status Data
VA
VA
Data
RY/BY
Notes : * The timings are similar to synchronous read timings. * VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. * RY/BY is active with data (A18 = 0 in the Burst Mode Configuration Register). When A18 = 1 in the Burst Mode Configuration Register, RY/BY is active one clock cycle before data.
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MB84SF6H6H6L2-70
* Example of Wait States Insertion (Non-Handshaking Device)
Data
D0
D1
ADV
Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following ADV falling edge
OE
1 2 3
4
5
6
7
CLK
0 1 2 3 4 5
number of clock cycles programmed
Wait State Decoding Addresses: A14, A13, A12 = "101" 5 programmed, 7 total A14, A13, A12 = "100" 4 programmed, 6 total A14, A13, A12 = "011" 3 programmed, 5 total A14, A13, A12 = "010" 2 programmed, 4 total A14, A13, A12 = "001" 1 programmed, 3 total A14, A13, A12 = "000" 0 programmed, 2 total Note : Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to "101".
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MB84SF6H6H6L2-70
* Bank-to-Bank Read/Write Cycle Timings
Last Cycle in Program or Sector Erase Command Sequence tWC Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence
tRC tCEPH
tRC
tWC
CEf
OE
tOE tOEH tGHWL
WE
tWPH tWP tDS tDH tACC tOEZ tOEH RD tSR/W RA RA 555h RD AAh
Data
tAS tAH
PD/30h
Address
PA/SA
ADV
Note : Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" while checking the status of the program or erase operation in the "busy" bank. The system should read status twice to ensure valid information.
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MB84SF6H6H6L2-70
s 128M FCRAM CHARACTERISTICS for MCP
1. State Diagram * Initial/Standby State Power Up Asynchronous Operation (Page Mode) Synchronous Operation (Burst Mode) CR Set Common State Power Down
Pause Time Power Down CE2r = H Standby
@M = 1
@M = 0
CE2r = H Standby
CE2r = L
CE2r = L
* Asynchronous Operation
CE2r = CE1r = H
Standby
CE1r = L & WE = L
CE1r = L
CE1r = H CE1r = H
CE1r = L & OE = L
CE1r = H WE = H
Output Disable
OE = L OE = H
WE = L Byte Control
Write
Byte Control @OE = L CE2r = CE1r = H Standby CE1r = H CE1r = H CE1r = L, ADV Low Pulse, & WE = L
Read
Address Change or Byte Control
* Synchronous Operation
CE1r = H
Write Suspend
CE1r = H CE1r = L, ADV Low Pulse, & OE = L
Read Suspend OE = L
WE = H WE = L ADV Low Pulse Write
OE = H
Read ADV Low Pulse (@BL = 8 or 16, and after burst operationis completed)
ADV Low Pulse
Note : Assuming all the parameters specified in "3. AC Characteristics" in "s 128M FCRAM CHARACTERISTICS for MCP" are satisfied. Refer to "2. Functial Description" and "3. AC Characteristics" for details. 54
MB84SF6H6H6L2-70
2. Functional Description This device supports asynchronous page read & normal write operation and synchronous burst read & burst write operation for faster memory access and features three kinds of power down modes for power saving as user configuable option. * Power-up It is required to follow the power-up timing to start executing proper device operation. Refer to POWER-UP Timing. After Power-up, the device defaults to asynchronous page read & normal write operation mode with sleep power down feature. * Configuration Register The Configuration Register (CR) is used to configure the type of device function among optional features. Each selection of features is set through CR Set sequence after Power-up. If CR Set sequence is not performed after power-up, the device is configured for asynchronous operation with sleep power down feature as default configuration. * CR Set Sequence The CR Set requires total 6 read/write operation with unique address. Between each read/write operation requires that device being in standby mode. Following table shows the detail sequence. Cycle # 1st 2nd 3rd 4th 5th 6th Operation Read Write Write Write Write Read Address 7FFFFFh (MSB) 7FFFFFh 7FFFFFh 7FFFFFh 7FFFFFh Address Key Data Read Data (RDa) RDa RDa X X Read Data (RDb)
The first cycle is to read from most significant address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the second or third cycle is written into the different address, the CR Set is cancelled and the data written by the second or third cycle is valid as a normal write operation. The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle is don't-care. If the forth or fifth cycle is written into different address, the CR Set is also cancelled but write data may not be written as normal write operation. The last cycle is to read from specific address key for mode selection. And read data (RDb) is invalid. Once this CR Set sequence is performed from an initial CR set to the other new CR set, the written data stored in memory cell array may be lost. So, it should perform the CR Set sequence prior to regular read/write operation if necessary to change from default configuration.
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* Address Key The address key has the following format. Address Pin A22 to A21 Register Name -- Function -- Partial Size Key 1 00 01 10 11 000 001 010 011 100 101 110 111 0 A15 M Mode 1 000 001 010 011 1xx 0 1 0 1 0 1 1 0 A7 A6 to A0 WC -- Write Control 1 -- 1 Description Unused bits must be 1 32M Partial 16M Partial Reserved for future use Sleep [Default] Reserved for future use Reserved for future use 8 words 16 words Reserved for future use Reserved for future use Reserved for future use Continuous Synchronous Mode (Burst Read / Write) Asynchronous Mode[Default] (Page Read / Normal Write) Reserved for future use 3 clocks 4 clocks 5 clocks Reserved for future use Reserved for future use Sequential Burst Read & Burst Write Burst Read & Single Write Falling Clock Edge Rising Clock Edge Unused bits muse be 1 WE Single Clock Pulse Control without Write Suspend Function WE Level Control with Write Suspend Function Unused bits must be 1 Note *1
A20 to A19
PS
*2 *2 *2
A18 to A16
BL
Burst Length
*2 *2 *2 *3 *4 *2
A14 to A12
RL
Read Latency
A11 A10 A9 A8
BS SW VE --
Burst Sequence Single Write Valid Clock Edge --
*2 *2
*5
*1 *5
*1
*1 : A22, A21, A8, and A6 to A0 must be all "1" in any cases. *2 : It is prohibited to apply this key. *3 : If M=0, all the registers must be set with appropriate Key input at the same time. *4 : If M=1, PS must be set with appropriate Key input at the same time. Except for PS, all the other key inputs must be "1". *5 : Burst Read & Single Write is not supported at WE Single Clock Pulse Control. 56
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* Power Down The Power Down is low power idle state controlled by CE2r. CE2r Low drives the device in power down mode and mains low power idle state as long as CE2r is kept low. CE2r High resume the device from power down mode. This device has three power down modes, Sleep, 16M Partial, and 32M Partial. The selection of power down mode is set through CR Set sequence. Each mode has following data retention features. Mode Sleep [default] 16M Partial 32M Partial Data Retention Size No 16M bit 32M bit Retention Address N/A 000000h to 0FFFFFh 000000h to 1FFFFFh
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to perform CR Set sequence to set to Sleep mode after power-up in case of asynchronous operation.
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* Burst Read/Write Operation Synchronous burst read/write operation provides faster memory access that synchronized to microcontroller or system bus frequency. Configuration Register Set is required to perform burst read & write operation after powerup. Once CR Set sequence is performed to select synchronous burst mode, the device is configured to synchronous burst read/write operation mode with corresponding RL and BL that is set through CR Set sequence together with operation mode. In order to perform synchronous burst read & write operation, it is required to control new signals, CLK, ADV and WAIT that Low Power SRAMs don't have. * Burst Read Operation CLK ADDRESS ADV CE1r OE High WE DQ High-Z RL Q1 BL WAIT High-Z Q2 QBL Valid
* Burst Write Operation CLK ADDRESS ADV CE1r High OE WE DQ High-Z RL-1 D1 BL WAIT High-Z D2 DBL Valid
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* CLK Input Function The CLK is input signal to synchronize memory to microcontroller or system bus frequency during synchronous burst read & write operation. The CLK input increments device internal address counter and the valid edge of CLK is referred for latency counts from address latch, burst write data latch, and burst read data out. During synchronous operation mode, CLK input must be supplied except for standby state and power down state. CLK is don't care during asynchronous operation. * ADV Input Function The ADV is input signal to indicate valid address presence on address inputs. It is applicable to synchronous operation as well as asynchronous operation. ADV input is active during CE1r = L and CE1r = H disables ADV input. All the address are determined on the positive edge of ADV. During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to High after valid address latch, it is inhibited to bring ADV Low until the end of burst or until burst operation is terminated. ADV Low pulse is mandatory for synchronous burst read/write operation mode to latch the valid address input. During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during asynchronous operation and it is not necessary to control ADV to High. * WAIT Output Function The WAIT is output signal to indicate data bus status when the device is operating in synchronous burst mode. During burst read operation, WAIT output is enabled after specified time duration from OE = L. WAIT output Low indicates data out at next clock cycle is invalid, and WAIT output becomes High one clock cycle prior to valid data out. During OE read suspend, WAIT output doesn't indicate data bus status but carries the same level from previous clock cycle (kept High) except for read suspend on the final data output. If final read data out is suspended, WAIT output become high impedance after specified time duration from OE = H. During burst write operation, WAIT output is enabled to High level after specified time duration from WE = L and kept High for entire write cycles including WE write suspend. The actual write data latching starts on the appropriate clock edge with respect to Valid Click Edge, Read Latency and Burst Length. During WE write suspend, WAIT output doesn't indicate data bus status but carries the same level from previous clock cycle (kept High) except for write suspend on the final data input. If final write data in is suspended, WAIT output become high impedance after specified time duration from WE = H. This device doesn't incur additional delay against accrossing device-row boundary or internal refresh orepation. Therefore, the burst operation is always started after fixed latency with respect to Read Latency. And there is no WAITting cycle asserted in the middle of burst operation except for burst suspend by OE brought to High or WE brought to High. Thus, once WAIT output is enabled and brought to High, WAIT output keep High level until the end of burst or until the burst operation is terminated. When the device is operating in asynchronous mode, WAIT output is always in High Impedance.
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* Latency Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. It is set through CR Set sequence after power-up. Once specific RL is set through CR Set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to RL-1. The burst operation is always started after fixed latency with respect to Read Latency set in CR. CLK ADDRESS ADV CE1r OE or WE RL = 3 DQ [Out] WAIT DQ [In] WAIT High-Z RL = 4 DQ [Out] WAIT DQ [In] WAIT High-Z RL = 5 DQ [Out] WAIT DQ [In] WAIT High-Z High-Z D1 D2 D3 D4 Q1 Q2 Q3 High-Z D1 D2 D3 D4 D5 Q1 Q2 Q3 Q4 High-Z D1 D2 D3 D4 D5 D5 Q1 Q2 Q3 Q4 Q5 0 Valid 1 2 3 4 5 6
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* Address Latch by ADV The ADV indicates valid address presence on address inputs. During synchronous burst read/write operation mode, all the address are determined on the positive edge of ADV when CE1r = L. The specified minimum value of ADV = L setup time and hold time against valid edge of clock where RL count begin must be satisfied for appropriate RL counts. Valid address must be determined with specified setup time against either the negative edge of ADV or negative edge of CE1r whichever comes late. And the determined valid address must not be changed during ADV = L period. * Burst Length Burst Length is the number of word to be read or write during synchronous burst read/write operation as the result of a single address latch cycle. It can be set on 8, 16 words boundary or continuous for entire address through CR Set sequence. The burst type is sequential that is incremental decoding scheme within a boundary address. Starting from initial address being latched, device internal address counter assign +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address (= 0). After completing read data out or write data latch for the set burst length, operation automatically ended except for continuous burst length. When continuous burst length is set, read/write is endless unless it is terminated by the positive edge of CE1r. * Single Write Single Write is synchronous write operation with Burst Length =1. The device can be configured either to "Burst Read & Single Write" or to "Burst Read & Burst Write" through CR set sequence. Once the device is configured to "Burst Read & Single Write" mode, the burst length for syncronous write operation is always fixed 1 regardless of BL values set in CR, while burst length for read is in accordance with BL values set in CR. * Write Control The device has two type of WE singal control method, "WE Level Control" and "WE Single Clock Pulse Control", for synchronous write operation. It is configured through CR set sequence. CLK ADDRESS ADV CE1r WE Level Control WE DQ [In] WAIT High-Z tWLTV tWLD D1 D2 D3 D4 RL = 5 0 Valid 1 2 3 4 5 6
WE Single Clock Pulse Control WE
tWSCK tCKWH
DQ [In] tWLTV WAIT High-Z
D1
D2
D3
D4
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* Burst Read Suspend Burst read operation can be suspended by OE High pulse. During burst read operation, OE brought to High suspends burst read operation. Once OE is brought to High with the specified set up time against clock where the data being suspended, the device internal counter is suspended, and the data output become high impedance after specified time duration. It is inhibited to suspend the first data out at the beginning of burst read. OE brought to Low resumes burst read operation. Once OE is brought to Low, data output become valid after specified time duration, and internal address counter is reactivated. The last data out being suspended as the result of OE = H and first data out as the result of OE = L are the from the same address. CLK tCKOH tOSCK OE tCKOH tOSCK
tAC DQ tCKTV WAIT Q1 tCKQX
tOHZ Q2 tOLZ
tAC
tAC Q2 tCKQX
tAC Q3 tCKQX Q4
* Burst Write Suspend Burst write operation can be suspended by WE High pulse. During burst write operation, WE brought to High suspends burst write operation. Once WE is brought to High with the specified set up time against clock where the data being suspended, device internal counter is suspended, data input is ignored. It is inhibited to suspend the first data input at the beginning of burst write. WE brought to Low resumes burst write operation. Once WE is brought to Low, data input become valid after specified time duration, and internal address counter is reactivated. The write address of the cycle where data being suspended and the first write address as the result of WE = L are the same address. Burst write suspend function is available when the device is operating in WE level controlled burst write only. CLK tCKWH tWSCK WE tCKWH tWSCK
tDSCK tDSCK DQ D1 tDHCK WAIT High D2 D2 tDHCK
tDSCK D3 tDHCK D4
tDSCK
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* Burst Read Termination Burst read operation can be terminated by CE1r brought to High. If BL is set on Continuous, burst read operation is continued endless unless terminated by CE1r = H. It is inhibited to terminate burst read before first data out is completed. In order to guarantee last data output, the specified minimum value of CE1r = L hold time from clock edge must be satisfied. After termination, the specified minimum recovery time is required to start new access. CLK ADDRESS ADV tCKCLH CE1r tCKOH OE WAIT DQ tAC Q1 Q2 High-Z tCKQX tOHZ tCHZ tTRB Valid
* Burst Write Termination Burst write operation can be terminated by CE1r brought to High. If BL is set on Continuous, burst write operation is continued endless unless terminated by CE1r = H. It is inhibited to terminate burst write before first data in is completed. In order to guarantee last write data being latched, the specified minimum values of CE1r = L hold time from clock edge must be satisfied. After termination, the specified minimum recovery time is required to start new access. CLK ADDRESS ADV tCKCLH CE1r tCKWH WE WAIT DQ tDSCK D1 tDHCK tDSCK D2 tDHCK High-Z tCHZ tTRB Valid
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3. AC Characteristics (Under Recommended Operating Conditions unless otherwise noted) * Asynchronous Read Operation (Page mode) Parameter Read Cycle Time CE1r Access Time OE Access Time Address Access Time ADV Access Time LB, UB Access Time Page Address Access Time Page Read Cycle Time Output Data Hold Time CE1r Low to Output Low-Z OE Low to Output Low-Z LB, UB Low to Output Low-Z CE1r High to Output High-Z OE High to Output High-Z LB, UB High to Output High-Z Address Setup Time to CE1r Low Address Setup Time to OE Low ADV Low Pulse Width Address Hold Time from ADV High Address Invalid Time Address Hold Time from CE1r High Address Hold Time from OE High CE1r High Pulse Width Symbol tRC tCE tOE tAA tAV tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tVPL tAHV tAX tCHAH tOHAH tCP -- -- 20 5 5 0 0 -- -- -- -5 10 10 5 -- -5 -5 15 Value Min 70 -- -- -- Max 1000 70 40 70 70 30 20 1000 -- -- -- -- 20 20 20 -- -- -- -- 10 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *5, *9 *10 *8 Notes *1, *2 *3 *3 *3, *5 *3 *3 *3, *6 *1, *6, *7 *3 *4 *4 *4 *3 *3 *3
*1 : Maximum value is applicable if CE1r is kept at Low without change of address input of A3 to A22. If needed by system operation, please contact local FUJITSU representative for the relaxation of 1s limitation. *2 : Address should not be changed within minimum tRC. *3 : The output load 50 pF with 50 termination to VCCQr x 0.5 V. *4 : The output load 5pF without any other load. *5 : Applicable to A3 to A22 when CE1r is kept at Low. *6 : Applicable only to A0, A1 and A2 when CE1r is kept at Low for the page address access. *7 : In case Page Read Cycle is continued with keeping CE1r stays Low, CE1r must be brought to High within 4 s. In other words, Page Read Cycle must be closed within 4 s. *8 : tVPL is specified from the negative edge of either CE1r or ADV whichever comes late. *9 : Applicable when at least two of address inputs among applicable are switched from previous state. *10 : tRC (Min) and tPRC (Min) must be satisfied. 64
MB84SF6H6H6L2-70
* Asynchronous Write Operation Value Parameter Write Cycle Time Address Setup Time ADV Low Pulse Width Address Hold Time from ADV High CE1r Write Pulse Width WE Write Pulse Width LB, UB Write Pulse Width CE1r Write Recovery Time WE Write Recovery Time LB, UB Write Recovery Time Data Setup Time Data Hold Time OE High to CE1r Low Setup Time for Write OE High to Address Setup Time for Write LB, UB Write Pulse Overlap CE1r High Pulse Width Symbol Min tWC tAS tVPL tAHV tCW tWP tBW tWRC tWR tBR tDS tDH tOHCL tOES tBWO tCP 70 0 10 5 45 45 45 15 15 15 15 0 -5 0 30 15 Max 1000 -- -- -- -- -- -- -- 1000 1000 -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *6 *7 *3 *3 *3 *5 *5 *5 *1, *2 *3 *4 Unit Notes
*1 : Maximum value is applicable if CE1r is kept at Low without any address change. If the relaxation is needed by system operation, please contact local FUJITSU representative for the relaxation of 1s limitation. *2 : Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWRC, tWR or tBR). *3 : Write pulse is defined from High to Low transition of CE1r, WE or LB / UB, whichever occurs last. *4 : tVPL is specified from the negative edge of either CE1r or ADV whichever comes late. *5 : Write recovery is defined from Low to High transition of CE1r, WE or LB / UB, whichever occurs first. *6 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns after CE1r is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. *7 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data bus is in High-Z.
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* Synchoronous Operation - Clock Input (Burst mode) Value Parameter RL = 5 Clock Period RL = 4 RL = 3 Clock High Time Clock Low Time Clock Rise/Fall Time tCKH tCKL tCKT tCK Symbol Min 13 18 30 4 4 -- Max -- -- -- -- -- 3 ns ns ns ns ns ns *2 *1 *1 *1 Unit Notes
*1 : Clock period is defined between valid clock edge. *2 : Clock rise/fall time is defined between VIH Min and VIL Max.
* Synchronous Operation - Address Latch (Burst mode) Value Parameter Address Setup Time to ADV Low Address Setup Time to CE1r Low Address Hold Time from ADV High ADV Low Pulse Width ADV Low Setup Time to CLK ADV Low Setup Time to CE1r Low CE1 Low Setup Time to CLK ADV Low Hold Time from CLK Burst End ADV High Hold Time from CLK Symbol Min tASVL tASCL tAHV tVPL tVSCK tVLCL tCLCK tCKVH tVHVL -5 -5 5 10 5 5 5 1 13 Max -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns *2 *3 *1 *3 *3 *1 *1 Unit Notes
*1 : tASCL is applicable if CE1 brought to Low after ADV is brought to Low under the condition where tVLCL is satisfied. The both of tASCL and tASVL must be satisfied if tVLCL is not satisfied. *2 : tVPL is specified from the negative edge of either CE1 or ADV whichever comes late. *3 : Applicable to the 1st valid clock edge.
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MB84SF6H6H6L2-70
* Synchronous Read Operation (Burst mode) Value Parameter Burst Read Cycle Time CLK Access Time Output Hold Time from CLK CE1r Low to WAIT Low OE Low to WAIT Low ADV Low to WAIT Low CLK to WAIT Valid Time WAIT Valid Hold Time from CLK CE1r Low to Output Low-Z OE Low to Output Low-Z LB, UB Low to Output Low-Z CE1r High to Output High-Z OE High to Output High-Z LB, UB High to Output High-Z CE1r High to WAIT High-Z OE High to WAIT High-Z OE Low Setup Time to 1st Data-out UB, LB Setup Time to 1st Data-out OE Setup Time to CLK OE Hold Time from CLK Burst End CE1r Low Hold Time from CLK Burst End UB, LB Hold Time from CLK BL = 8,16 Burst Terminate Recovery Time BL = Continuous *1 : The output load 50 pF with 50 termination to VCCQr x 0.5 V. *2 : The output load 5 pF without any other load. *3 : Once they are determined, they must not be changed until the end of burst. *4 : Defined from the Low to High transition of CE1r to the High to Low transition of either ADV or CE1r whichever occurs late. tTRB 70 -- ns *4 Symbol Min tRCB tAC tCKQX tCLTL tOLTL tVLTL tCKTV tCKTX tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tCHTZ tOHTZ tOLQ tBSQ tOSCK tCKOH tCKCLH tCKBH -- -- 3 5 0 0 -- 3 5 0 0 -- -- -- -- -- 30 26 5 5 5 5 26 Max 8000 11 -- 20 20 20 11 -- -- -- -- 20 20 20 20 20 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *4 *3 *1 *1 *1 *1 *1 *1 *1 *2 *2 *2 *1 *1 *1 *1 *1 Unit Notes
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* Synchronous Write Operation (Burst mode) Value Parameter Burst Write Cycle Time Data Setup Time to Clock Data Hold Time from CLK WE Low Setup Time to 1st Data In UB, LB Setup Time for Write WE Setup Time to CLK WE Hold Time from CLK CE1r Low to WAIT High WE Low to WAIT High CE1r High to WAIT High-Z WE High to WAIT High-Z Burst End CE1r Low Hold Time from CLK Burst End CE1r High Setup Time to next CLK Burst End UB, LB Hold Time from CLK Burst Write Recovery Time BL = 8,16 Burst Terminate Recovery Time BL = Continuous tTRB 70 -- ns *4 Symbol Min tWCB tDSCK tDHCK tWLD tBS tWSCK tCKWH tCLTH tWLTH tCHTZ tWHTZ tCKCLH tCHCK tCKBH tWRB tTRB -- 5 3 30 -5 5 5 5 0 -- -- 5 5 5 26 26 -- Max 8000 -- -- -- -- -- -- 20 20 20 20 -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *3 *4 *2 *2 *2 *2 *1 Unit Notes
*1 : Defined from the valid input edge to the High to Low transition of either ADV, CE1r, or WE, whichever occurs last. And once they are determined, they must not be changed until the end of burst. *2 : The output load 50 pF with 50 termination to VCCQr x 0.5 V. *3 : The output load 5 pF without any other load. *4 : Defined from the valid clock edge where last data-in being latched at the end of burst write to the High to Low transition of either ADV or CE1r whichever occurs late for the next access. *5 : Defined from the Low to High transition of CE1r to the High to Low transition of either ADV or CE1r whichever occurs late for the next access.
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* Power Down Parameters Value Parameter CE2r Low Setup Time for Power Down Entry CE2r Low Hold Time after Power Down Entry CE1r High Hold Time following CE2r High after Power Down Exit [SLEEP mode only] CE1r High Hold Time following CE2r High after Power Down Exit [not in SLEEP mode] CE1r High Setup Time following CE2r High after Power Down Exit *1 : Applicable also to power-up. *2 : Applicable when Partial mode is set. Symbol Min tCSP tC2LP tCHH tCHHP tCHS 20 70 300 1 0 Max -- -- -- -- -- ns ns s s ns *1 *1 *1 *2 *1 Unit Note
* Other Timing Parameters Value Parameter CE1r High to OE Invalid Time for Standby Entry CE1r High to WE Invalid Time for Standby Entry CE2r High Hold Time after Power-up CE1r High Hold Time following CE2r High after Power-up Input Transition Time (except for CLK) Symbol Min tCHOX tCHWX tC2HL tCHH tT 10 10 50 300 1 Max -- -- -- -- 25 ns ns s s ns *2, *3 *1 Unit Note
*1 : Some data might be written into any address location if tCHWX (Min) is not satisfied. *2 : Except for clock input transition time. *3 : The Input Transition Time (tT) at AC testing is shown in below. If actual tT is longer than specified values, it may violate AC specification of some timing parameters.
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MB84SF6H6H6L2-70
* AC Test Conditions Description Input High Level Input Low Level Input Timing Measurement Level Async. Input Transition Time Sync. tT Between VIL and VIH 3 ns Symbol VIH VIL VREF Test Setup -- -- -- Value VCCQr x 0.8 VCCQr x 0.2 VCCQr x 0.5 5 Unit V V V ns Note
* AC MEASUREMENT OUTPUT LOAD CIRCUIT VCCr x 0.5 V VCCr VSS VCCQr VSS 0.1 F DEVICE UNDER TEST 50 pF 50 OUT
0.1 F
70
MB84SF6H6H6L2-70
* Asynchronous Read Timing #1-1 (Basic Timing) tRC ADDRESS ADV Low tASC CE1r tOE OE tOHZ tBA LB / UB DQ (Output) tOLZ tBLZ tBHZ tCE tCHAH tCP tCHZ tASC ADDRESS VALID
VALID DATA OUTPUT Note : This timing diagram assumes CE2r = H and WE = H.
tOH
* Asynchronous Read Timing #1-2 (Basic Timing) tRC ADDRESS ADDRESS VALID tAV ADV tASC CE1r tOE OE tOHZ tBA LB / UB DQ (Output) tOLZ tBLZ tBHZ tVPL tCE tCP tCHZ tASC tAHV
VALID DATA OUTPUT Note : This timing diagram assumes CE2r = H and WE = H.
tOH
71
MB84SF6H6H6L2-70
* Asynchronous Read Timing #2 (OE & Address Access) tRC ADDRESS ADDRESS VALID tAA CE1r Low tASO OE LB / UB tOLZ DQ (Output) VALID DATA OUTPUT Note : This timing diagram assumes CE2r = H, ADV = L and WE = H. VALID DATA OUTPUT tOH tOH tOHZ tOE tAx tRC ADDRESS VALID tAA tOHAH
* Asynchronous Read Timing #3 (LB / UB Byte Access) tAX ADDRESS tAA CE1r, OE LB tBA UB tBLZ DQ7 to DQ0 (Output) DQ15 to DQ8 (Output) VALID DATA OUTPUT tBLZ VALID DATA OUTPUT tOH tBHZ tBHZ tOH tBLZ tBHZ tOH Low tBA tBA tRC ADDRESS VALID tAx
VALID DATA OUTPUT
Note : This timing diagram assumes CE2r = H, ADV = L and WE = H.
72
MB84SF6H6H6L2-70
* Asynchronous Read Timing #4 (Page Address Access after CE1r Control Access) tRC ADDRESS (A22 to A3) tRC ADDRESS (A2 to A0) tASC ADV CE1r tCHZ OE LB / UB tCLZ DQ (Output) VALID DATA OUTPUT (Normal Access) Note : This timing diagram assumes CE2r = H and WE = H. VALID DATA OUTPUT (Page Access) tOH tOH tOH tOH tCE ADDRESS VALID ADDRESS VALID tPRC
ADDRESS
tPRC
ADDRESS
tPRC ADDRESS tPAA tCHAH
tPAA
tPAA
* Asynchronous Read Timing #5 (Random and Page Address Access) tRC ADDRESS (A22 to A3) ADDRESS (A2 to A0) CE1r Low tASO OE tBA LB / UB DQ (Output)
tOLZ tBLZ tAX
tRC ADDRESS VALID
tAx
ADDRESS VALID tRC
ADDRESS VALID
tPRC
ADDRESS VALID
tRC
ADDRESS VALID
tPRC
ADDRESS VALID
tAA tOE
tPAA
tAA
tPAA
tOH
tOH
tOH
tOH
VALID DATA OUTPUT (Normal Access)
VALID DATA OUTPUT (Page Access)
Notes : * This timing diagram assumes CE2r = H, ADV = L and WE = H. * Either or both LB and UB must be Low when both CE1r and OE are Low. 73
MB84SF6H6H6L2-70
* Asynchronous Write Timing #1-1 (Basic Timing) tWC ADDRESS ADV Low tAS CE1r tAS WE tAS LB, UB tOHCL OE DQ (Input) VALID DATA INPUT Note : This timing diagram assumes CE2r = H and ADV = L. tDS tDH tBW tBR tAS tWP tWR tAS tCW tWRC tAS ADDRESS VALID
* Asynchronous Write Timing #1-2 (Basic Timing) tWC ADDRESS ADV tAS CE1r tAS WE tAS LB, UB tOHCL OE DQ (Input) VALID DATA INPUT Note : This timing diagram assumes CE2r = H. tDS tDH tBW tBR tAS tWP tWR tAS ADDRESS VALID
tVP04.3.12L
tAHV tCW tWRC tAS
74
MB84SF6H6H6L2-70
* Asynchronous Write Timing #2 (WE Control) tWC ADDRESS tOHAH CE1r Low tAS WE tWP tWR tAS tWP tWR ADDRESS VALID tWC ADDRESS VALID
LB, UB tOES OE tOHZ DQ (Input) VALID DATA INPUT Note : This timing diagram assumes CE2r = H and ADV = L. VALID DATA INPUT tDS tDH tDS tDH
* Asynchronous Write Timing #3-1 (WE / LB / UB Byte Write Control) tWC ADDRESS CE1r Low tAS WE tBR LB tBR UB tDS DQ0 to DQ7 (Input) DQ8 to DQ15 (Input) VALID DATA INPUT tDS tDH tDH tWP tAS tWP ADDRESS VALID tWC ADDRESS VALID
VALID DATA INPUT Note : This timing diagram assumes CE2r = H, ADV = L and OE = H.
75
MB84SF6H6H6L2-70
* Asynchronous Write Timing #3-2 (WE / LB / UB Byte Write Control) tWC ADDRESS CE1r Low tWR WE tAS LB tAS UB tDS DQ0 to DQ7 (Input) DQ8 to DQ15 (Input) VALID DATA INPUT tDH tBW tBW tWR ADDRESS VALID tWC ADDRESS VALID
tDS
tDH
VALID DATA INPUT Note : This timing diagram assumes CE2r = H, ADV = L and OE = H.
* Asynchronous Write Timing #3-3 (WE / LB / UB Byte Write Control) tWC ADDRESS CE1r Low ADDRESS VALID tWC ADDRESS VALID
WE tAS LB tAS UB tDS DQ0 to DQ7 (Input) VALID DATA INPUT DQ8 to DQ15 (Input) VALID DATA INPUT Note : This timing diagram assumes CE2r = H, ADV = L and OE = H. tDS tDH tDH tBW tBR tBW tBR
76
MB84SF6H6H6L2-70
* Asynchronous Write Timing #3-4 (WE / LB / UB Byte Write Control) tWC ADDRESS CE1r Low ADDRESS VALID tWC ADDRESS VALID
WE tAS LB tBWO DQ0 to DQ7 (Input) tAS UB
tDS tDH
tBW
tBR
tAS
tBW
tBR
tDS
tDH
tDS
tDH
VALID DATA INPUT
VALID DATA INPUT
tBW
tBR
tAS
tBWO tBW tDS
tBR
tDH
DQ8 to DQ15 (Input)
VALID DATA INPUT
VALID DATA INPUT
Note : This timing diagram assumes CE2r = H, ADV = L and OE = H. * Asynchronous Read / Write Timing #1-1 (CE1r Control) tWC ADDRESS tCHAH CE1r tCP WE tCP tAS WRITE ADDRESS tCW tWRC tASC tRC READ ADDRESS tCE tCHAH
UB, LB tOHCL OE tCHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT tDS tDH tCLZ tOH
Notes : * This timing diagram assumes CE2r = H and ADV = L. * Write address is valid from either CE1r or WE of last falling edge.
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MB84SF6H6H6L2-70
* Asynchronous Read / Write Timing #1-2 (CE1r / WE / OE Control) tWC ADDRESS tCHAH CE1r tCP WE tWP tCP tAS WRITE ADDRESS tWR tASC tRC READ ADDRESS tCE tCHAH
UB, LB tOHCL OE tCHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH
tOLZ
tOE tOH
Notes : * This timing diagram assumes CE2r = H and ADV = L. * OE can be fixed Low during write operation if it is CE1r controlled write at Read-Write-Read sequence.
* Asynchronous Read / Write Timing #2 (OE, WE Control) tWC ADDRESS tOHAH CE1r Low tAS WE tOES tWP tWR WRITE ADDRESS tRC READ ADDRESS tAA tOHAH
UB, LB tASO OE tOHZ tOH tDS tOE tOHZ tOH
tDH
tOLZ
DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT
Notes : * This timing diagram assumes CE2r = H and ADV = L. * CE1r can be tied to Low for WE and OE controlled operation.
78
MB84SF6H6H6L2-70
* Asynchronous Read / Write Timing #3 (OE, WE, LB, UB Control) tWC ADDRESS WRITE ADDRESS tOHAH tRC READ ADDRESS tAA CE1r Low tOHAH
WE tOES UB, LB
tBHZ
tAS
tBW
tBR tASO
tBA
OE tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tBLZ tBHZ tOH
Notes : * This timing diagram assumes CE2r = H and ADV = L. * CE1r can be tied to Low for WE and OE controlled operation.
* Clock Input Timing tCK CLK
tCK
tCKH
tCKL
tCKT
tCKT
Notes : * Stable clock input must be required during CE1r = L. * tCK is defined between valid clock edge. * tCKT is defined between VIH Min and VIL Max.
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MB84SF6H6H6L2-70
* Address Latch Timing (Synchronous Mode) Case #1 CLK Case #2
ADDRESS tASCL tVSCK ADV tVLCL tCLCK
Valid tCKVH tAHV tASVL tVSCK
Valid tCKVH tAHV
tVPL
tVPL
CE1r
Low
Notes : * Case #1 is the timing when CE1r is brought to Low after ADV is brought to Low. Case #2 is the timing when ADV is brought to Low after CE1r is brought to Low. * tVPL is specified from the negative edge of either CE1r or ADV whichever comes late. At least one valid clock edge must be input during ADV = L. * tVSCK and tCLCK are applied to the 1st valid clock edge during ADV = L.
80
MB84SF6H6H6L2-70
* Synchronous Read Timing #1 (OE Control) RL=5 CLK tRCB ADDRESS tASVL ADV tVPL tASCL CE1r tCLCK OE tOLQ WE High tCKBH tBLQ LB, UB tCKTV WAIT High-Z tOLTL DQ High-Z tOLZ tCKTX tAC tAC Q1 tCKQX tAC QBL tCKQX tOHZ tOHTZ tCKOH tCLCK tCP tVHVL tASCL tVPL Valid tVSCK tAHV tCKVH tASVL Valid tVSCK tCKVH
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
81
MB84SF6H6H6L2-70
* Synchronous Read Timing #2 (CE1r Control) RL=5 CLK tRCB ADDRESS tASVL ADV tVPL tASCL CE1r tCLCK tCKCLH OE tCP tCLCK tVHVL tASCL tVPL Valid tVSCK tAHV
tCKVH
Valid tASVL tVSCK tAHV tCKVH
WE
High tCKBH
LB, UB tCKTV WAIT tCLTL DQ tCLZ tCKTX tAC tAC Q1 tCKQX tAC QBL tCKQX tCHZ tCLZ tCHTZ tCLTL
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
82
MB84SF6H6H6L2-70
* Synchronous Read Timing #3 (ADV Control) RL = 5 CLK tRCB ADDRESS tASVL ADV tVPL tVHVL tVPL Valid tVSCK tAHV tCKVH tASVL Valid tVSCK tAHV tCKVH
CE1r
Low
OE
Low
WE
High
LB, UB tVLTL WAIT tCKTX DQ tAC tAC Q1 tCKQX tAC QBL tCKQX tCKTV tVLTL
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
83
MB84SF6H6H6L2-70
* Synchronous Write Timing #1 (WE Level Control) RL = 5 CLK tWCB ADDRESS tASVL ADV tVPL tASCL CE1r tCLCK OE High tWLD WE tBS LB, UB tCKBH tBS tCKWH tCP Valid tVSCK tAHV tCKVH tVHVL tWRB tASCL tASVL Valid tVSCK tAHV tCKVH tVPL tCLCK
WAIT
High-Z tWLTH tDSCK D1 tDHCK tDSCK D2 tDSCK DBL tDHCK tWHTZ
DQ
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
84
MB84SF6H6H6L2-70
* Synchronous Write Timing #2 (WE Single Clock Pulse Control) RL = 5 CLK tWCB ADDRESS tASVL ADV tVPL tASCL CE1r tCLCK OE High tWSCK WE tBS LB, UB tCKBH tBS tCKWH tWSCK tCKWH tCP tCKCLH Valid tVSCK tAHV tCKVH tVHVL tWRB tASCL tASVL Valid tVSCK tAHV tCKVH tVPL tCLCK
WAIT
High-Z tWLTH tDSCK D1 tDHCK tDSCK D2 tDSCK DBL tDHCK tCHTZ tWLTH
DQ
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
85
MB84SF6H6H6L2-70
* Synchronous Write Timing #3 (ADV Control) RL = 5 CLK tWCB ADDRESS tASVL ADV tVPL Valid tVSCK tAHV tCKVH tVHVL tASVL Valid tVSCK tAHV tCKVH tVPL
CE1r
tWRB
OE
High
WE tBS LB, UB tCKBH tBS
High WAIT tDSCK DQ D1 tDHCK tDSCK D2 tDSCK DBL tDHCK
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
86
MB84SF6H6H6L2-70
* Synchronous Write Timing #4 (WE Level Control, Single Write) RL = 5 CLK tWCB ADDRESS tASVL ADV tVPL tASCL CE1r tCLCK OE High tWLD WE tBS LB, UB tCKBH tBS tCKWH tCP Valid tVSCK tAHV tCKVH tVHVL tWRB tASCL tASVL Valid tVSCK tAHV tCKVH tVPL tCLCK
WAIT
High-Z tWLTH tDSCK D1 tDHCK tWHTZ tWLTH
DQ
Notes : * This timing diagram assumes CE2r = H, the valid clock edge on rising edge and single write operation. * Write data is latched on the valid clock edge.
87
MB84SF6H6H6L2-70
* Synchronous Read to Write Timing #1 (CE1 Control) RL = 5 CLK tWCB ADDRESS tASVL ADV tCKCLH CE1r tCP OE Valid tVSCK tAHV tCKVH tVPL tCLCK tCKCLH
tVHVL tASCL
WE tCKBH LB, UB tCHTZ WAIT tAC DQ QBL-1 tCKQX QBL tCKQX tCHZ tCLTH tDSCK D1 tDHCK tDSCK D2 tDHCK tDSCK D3 tDHCK tDSCK DBL tDHCK tBS tCKBH
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
88
MB84SF6H6H6L2-70
* Synchronous Read to Write Timing #2(ADV Control) RL = 5 CLK
ADDRESS tASVL ADV
Valid tVSCK tAHV tCKVH tVPL tVHVL
CE1r
tCKOH OE tWLD tCKWH
WE tCKBH LB, UB tOHTZ WAIT tAC DQ QBL-1 tCKQX QBL tCKQX tOHZ tWLTH tDSCK D1 tDHCK tDSCK D2 tDHCK tDSCK D3 tDHCK tDSCK DBL tDHCK tBS tCKBH
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
89
MB84SF6H6H6L2-70
* Synchronous Write to Read Timing #1 (CE1r Control) RL=5 CLK
ADDRESS tASVL ADV
Valid tVSCK tAHV tCKVH tVPL tCKCLH tASCL tCP tWRB tCLCK
CE1r
OE
WE tCKBH LB, UB tCKTV WAIT tDSCK DQ tDSCK DBL tDHCK tCLZ tCHTZ High-Z tCLTL tCKTX tAC tAC Q1 tCKQX Q2 tCKQX
DBL-1 tDHCK
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
90
MB84SF6H6H6L2-70
* Synchronous Write to Read Timing #2 (ADV Control) RL = 5 CLK
ADDRESS tASVL ADV tWRB CE1r Low
Valid tVSCK tAHV tCKVH tVPL
OE tCKWH WE tCKBH LB, UB tCKTV WAIT tDSCK DQ tDSCK DBL tDHCK tOLZ tWHTZ High-Z tOLTL tCKTX tAC tAC Q1 tCKQX Q2 tCKQX tBLQ tOLQ
DBL-1 tDHCK
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
91
MB84SF6H6H6L2-70
* POWER-UP Timing #1
CE1r
*2 tCHH*3
CE2r
*2
VCCQr 0V VCCr 0V
VCCQ Min*1
VCC Min*1,*2
*1 : VCCQr shall be applied and reach the specified minimum level prior to VCCr applied. *2 : The both of CE1r and CE2r shall be brought to High together with VCCQr prior to VCCr applied. Otherwise POWER-UP Timing#2 must be applied for proper operation. *3 : The tCHH specifies after VCCr reaches specified minimum level and applicable to both CE1r and CE2r.
* POWER-UP Timing #2
CE1r
*3 tCHS tC2HL*2 tCSP tC2LP tCHH
CE2r tC2HL*2 VCCQr 0V VCCr 0V *1 : VCCQr shall be applied and reach specified minimum level prior to VCC applied. *2 : The tC2HL specifies from CE2r Low to High transition after VCCr reaches specified minimum level. If CE2r became High prior to VCCr reached specified minimum level, tC2HL is defined from VCCr minimum. *3 : CE1r shall be brought to High prior to or together with CE2r Low to High transition. VCCr Min*1 VCCQr Min*1
92
MB84SF6H6H6L2-70
* POWER DOWN Entry and Exit Timing
CE1r tCHS CE2r tCSP DQ Power Down Entry tC2LP High-Z Power Down Mode Power Down Exit tCHH (tCHHP)
Note : This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and Power-Down program was not performed prior to this reset.
* Standby Entry Timing after Read or Write
CE1r tCHOX OE tCHWX
WE Active (Read) Standby Active (Write) Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period for Standby mode from CE1r Low to High transition.
93
MB84SF6H6H6L2-70
* Configuration Register Set Timing #1 (Asynchronous Operation)
tRC ADDRESS MSB*1 tCP CE1r
tWC MSB*1 tCP
tWC MSB*1 tCP
tWC MSB*1 tCP
tWC MSB*1 tCP
tWC Key*2
tCP*3 (tRC)
OE
WE
LB, UB
DQ*3
RDa Cycle #1
RDa Cycle #2
RDa Cycle #3
X Cycle #4
X Cycle #5
RDb Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #5. *2 : The address key must confirm the format specified in FUNCTIONAL DESCRIPTION. If not, the operation and data are not guaranteed. *3 : After tCP or tRC following Cycle #6, the Configuration Register Set is completed and returned to the normal operation. tCP and tRC are applicable to returning to asynchronous mode and to synchronous mode respectively.
94
MB84SF6H6H6L2-70
* WE Configuration Register Set Timing #2 (Synchronous Operation)
CLK
ADDRESS MSB tRCB ADV tTRB CE1r
MSB
MSB
MSB
MSB
Key
tWCB
tWCB
tWCB
tWCB
tRCB
tTRB
tTRB
tTRB
tTRB
tTRB
OE
WE
LB, UB RL DQ
RDa
RL-1
RDa
RL-1
RDa
RL-1 X Cycle#4
RL-1 X Cycle#5
RL
RDb
Cycle#1
Cycle#2
Cycle#3
Cycle#6
Notes : * The all address inputs must be High from Cycle #1 to #5. * The address key must confirm the format specified in FUNCTIONAL DESCRIPTION. If not, the operation and data are not guaranteed. * After tTRB following Cycle #6, the Configuration Register Set is completed and returned to the normal operation.
95
MB84SF6H6H6L2-70
s PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Condition VIN = 0 VOUT = 0 VIN = 0 Value Min Typ Max 20.0 25.0 25.0 Unit pF pF pF
Note: Test conditions TA = +25C, f = 1.0 MHz
s HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
s CAUTION
* The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET. * Without the high voltage (VID) , sector group protection can be achieved by using "Extended Sector Group Protection" command.
96
MB84SF6H6H6L2-70
s ORDERING INFORMATION
MB84SF6H6H6L 2 -70 PBS
PACKAGE TYPE PBS = 115-ball BGA
SPEED OPTION
Device Revision
DEVICE NUMBER/DESCRIPTON 128Mega-bit (8M x 16bit) Burst Flash Memory 1.8V-only Read, Program, and Erase 128Mega-bit (8M x 16bit) Burst Flash Memory 1.8V-only Read, Program, and Erase 128 Mega-bit (8M x 16bit) FCRAM 1.8V I/O Supply Voltage 3.0V Core Supply Voltage
97
MB84SF6H6H6L2-70
s PACKAGE DIMENSION
115-ball plastic FBGA (BGA-115P-M03)
12.000.10(.472.004) 0.20(.008) S B 1.250.10 (Seated height) (.049.004) 0.80(.031) REF A 9.000.10 (.354.004)
B 0.40(.016) REF 0.80(.031) REF 10 9 8 7 6 5 4 3 2 1 PNMLKJHGFEDCBA
+.010
0.40(.016) REF 0.08(.003) S
INDEX-MARK AREA
0.100.05 (Stand off) (.004.002) S
115-o0.40 -0.05 0.20(.008) S A 115-o.016
+.004 -.002
o0.08(.003)
M
SAB
0.08(.003) S
C
2003 FUJITSU LIMITED B115003S-c-1-1
Dimensions in mm (inches) Note : The values in parentheses are reference values.
98
MB84SF6H6H6L2-70
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0403 (c) FUJITSU LIMITED Printed in Japan

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